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公开(公告)号：EP1788765A1
公开(公告)日：2007-05-23
申请号：EP05425816.5
申请日：2005-11-18
Applicant: STMicroelectronics S.r.l.
Inventor： Vimercati, Daniele , Nava, Claudio , Laurent, Christophe
CPC classification number: H04L25/0266 , H04B3/56 , H04B2203/5487
Abstract: A transmission system of a digital signal is described of the type comprising a transmitter and a receiver connected by means of a transfer bus. The transmission system comprises at least one conductive line capacitively coupled with said transfer bus.
Abstract translation: 描述了数字信号的传输系统，其类型包括通过传输总线连接的发射机和接收机。 传输系统包括与所述传输总线电容耦合的至少一个导线。
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2.发明公开
公开(公告)号：EP1049100A1
公开(公告)日：2000-11-02
申请号：EP99830253.3
申请日：1999-04-28
Applicant: STMicroelectronics S.r.l.
Inventor： Bartoli, Simone , Sali, Mauro , Nava, Claudio , Russo, Antonio
CPC classification number: G11C7/10 , G11C5/04 , G11C5/063 , G11C2207/105
Abstract: Semiconductor device comprising at least two pads (101, 102; 103, 104) for the input of external signals and/or for the output of signals from said semiconductor device, at least two uncoupling buffers (201, 202; 203, 204) each connected to each one of said pads, at least one multiplexer (10; 20) connected to said pads (101, 102; 103, 104) by means of said uncoupling buffers (201, 202; 203, 204) and at least one memory element (4; 5) suitable to generate a configuration signal (C ) operating on said multiplexer (10; 20) and said uncoupling buffers (201, 202; 203, 204) to selectively enable one or the other of said pads (101, 102; 103, 104).
Abstract translation: 半导体器件包括用于输入外部信号和/或用于从所述半导体器件输出信号的至少两个焊盘（101,102; 103,104），至少两个解耦缓冲器（201,202; 203,204） 连接到所述焊盘中的每一个，至少一个通过所述解耦缓冲器（201,202; 203,204）连接到所述焊盘（101,102; 103,104）的多路复用器（10; 20）和至少一个存储器 元件（4; 5），适于产生在所述多路复用器（10; 20）和所述非耦合缓冲器（201,202; 203,204）上操作的配置信号（C），以选择性地使得所述焊盘 102; 103，104）。
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公开(公告)号：EP1049100B1
公开(公告)日：2005-01-19
申请号：EP99830253.3
申请日：1999-04-28
Applicant: STMicroelectronics S.r.l.
Inventor： Bartoli, Simone , Sali, Mauro , Nava, Claudio , Russo, Antonio
CPC classification number: G11C7/10 , G11C5/04 , G11C5/063 , G11C2207/105
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4.发明公开
公开(公告)号：EP1221771A1
公开(公告)日：2002-07-10
申请号：EP01830005.3
申请日：2001-01-08
Applicant: STMicroelectronics S.r.l.
Inventor： Sforzin, Marco , Bedarida, Lorenzo , Defendi, Marco , Nava, Claudio
IPC: H03K17/16
CPC classification number: H03K19/00361 , H03K17/163
Abstract: The output-buffer circuit (1) comprises an end stage (2) made up of a pull-up transistor (3) and a pull-down transistor (4) connected in series between a supply line (5) and a ground line (GND); a first driving stage (8) connected to a control terminal of the pull-up transistor (3) and comprising a plurality of first driving branches (12) which can be selectively activated by a logic control circuit (16) according to the reading and operating modes of a memory device (100) including the output-buffer circuit (1) and to the variability of the electrical parameters of the output-buffer circuit; and a second driving stage (9) connected to a control terminal of the pull-down transistor (4) and comprising a plurality of second driving branches (22) which can also be selectively activated by the control circuit (16) according to the reading and operating modes of a memory device (100) including the output-buffer circuit (1) and to the variability of the electrical parameters of the output-buffer circuit.
Abstract translation: 输出缓冲电路（1）包括由串联连接在电源线（5）和接地线（5）之间的上拉晶体管（3）和下拉晶体管（4）构成的端级（2） GND）; 第一驱动级（8），连接到所述上拉晶体管（3）的控制端，并且包括多个第一驱动分支（12），所述第一驱动分支可根据所述读取被逻辑控制电路（16）选择性地激活;以及 包括输出缓冲器电路（1）的存储器件（100）的工作模式以及输出缓冲器电路的电气参数的可变性; 以及连接到所述下拉晶体管（4）的控制端子并且包括多个第二驱动分支（22）的第二驱动级（9），所述第二驱动分支（22）还可以根据所述读取被所述控制电路（16）选择性地启动 以及包括输出缓冲器电路（1）的存储器件（100）的工作模式以及输出缓冲器电路的电气参数的变化。
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