公开(公告)号：EP1176603A1

公开(公告)日：2002-01-30

申请号：EP00830529.4

申请日：2000-07-26

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Emanuele ,  Bedarida, Lorenzo ,  Sali, Mauro ,  Bartoli, Simone

IPC: G11C16/30

CPC classification number: G11C16/30

Abstract: The memory comprises a matrix of cells (10), a charge pump (11), a voltage regulator, controllable connection elements (12) each connected between the output of the charge pump (11) and a column line of the matrix of cells, and means (14) for selectively activating the connection elements.
To arrange for the voltage of a cell in a predetermined biasing condition, for example, the programming condition, to be independent of temperature variations and of manufacturing and design parameters, the memory comprises a first element (12') equivalent to a connection element (12) and a second element (10') equivalent to a memory cell (10) in the predetermined biasing condition. These equivalent elements are connected in series with one another between the output terminal and the common terminal of the charge pump (11). The regulator (15, 17) is connected between the second equivalent element (10') and the input of the charge pump (11) in order to regulate the output voltage of the charge pump (11) in dependence on the voltage across the second equivalent element (10').

Abstract translation: 所述存储器包括单元的矩阵（10），一个电荷泵（11），电压调节器，可控制连接件（12），每个连接在所述电荷泵的输出端（11）和单元的矩阵的列线之间， 和装置（14），用于选择性激活所述连接元件。 安排在一个预定的偏状态的电池的电压，例如，编程条件，是独立的温度变化的和的制造和设计参数，所述存储器包括：第一元件（12“）等同于一个连接元件（ 12）以及等同于预定的偏状态的存储单元（10）的第二元件（10“）。 这些等效的元件被串联连接与所述输出端子和所述电荷泵（11）的公共端子之间彼此。 调节器（15，17），以便调节上横跨第二电压依赖的电荷泵（11）的输出电压连接在第二等效元件（10“）和所述电荷泵（11）的输入端之间 等效元件（10“）。

公开(公告)号：EP1071211A1

公开(公告)日：2001-01-24

申请号：EP99830467.9

申请日：1999-07-21

Applicant: STMicroelectronics S.r.l.

Inventor： Bedarida, Lorenzo ,  Disegni, Fabio ,  Dima, Vincenzo ,  Bartoli, Simone

IPC: H03K17/06 ,  H03K17/30

CPC classification number: H03K17/063 ,  H03K19/0027

Abstract: The present invention refers to a circuit disposal of a transistor shaped like a diode, in particular to a disposal able to reduce the threshold voltage of the transistor and equal to the difference of the threshold voltage of the used transistors in the circuit disposal.
In an embodiment the circuit disposal comprises a first pMOS transistor (300) having a second pMOS transistor (301) shaped like a diode connected between the gate and the drain of the first transistor and a current generator (310) connected to the gates of the two transistors. Such a circuitry disposal it is also applicable to a nMOS transistor. From a general point of view this invention refers to a nMOS or pMOS transistor whose gate voltage is increased (for the nMOS transistors) or decreased (for the pMOS transistors) by using a circuit in series to the gate that provides an opportune delta of voltage.

Abstract translation: 本发明涉及一种形状类似二极管的晶体管的电路处理，特别是涉及能够降低晶体管的阈值电压并等于电路处置中所用晶体管的阈值电压差的处理。 在一个实施例中，电路处理包括具有第二pMOS晶体管（301）的第一pMOS晶体管（300），第二pMOS晶体管（301）形成为类似于连接在第一晶体管的栅极和漏极之间的二极管，以及电流发生器（310） 两个晶体管。 这种电路处理也适用于nMOS晶体管。 从一般观点来看，本发明涉及通过使用串联提供电压的时间增量的电路的栅极电压增加（对于nMOS晶体管）或降低（对于pMOS晶体管）的nMOS或pMOS晶体管， 。

公开(公告)号：EP1103977B1

公开(公告)日：2009-02-25

申请号：EP99830722.7

申请日：1999-11-25

Applicant: STMicroelectronics S.r.l.

Inventor： Bartoli, Simone ,  Geraci, Antonino ,  Sali, Mauro ,  Bedarida, Lorenzo

IPC: G11C7/00

CPC classification number: G11C7/1033 ,  G11C7/1045 ,  G11C7/1072

公开(公告)号：EP1071094B1

公开(公告)日：2005-11-23

申请号：EP99830403.4

申请日：1999-06-25

Applicant: STMicroelectronics S.r.l.

Inventor： Bedarida, Lorenzo ,  Dima, Vincenzo ,  Brani, Francesco ,  Defendi, Marco

IPC: G11C7/14 ,  G11C16/28

CPC classification number: G11C16/28 ,  G11C7/14

公开(公告)号：EP1184873A1

公开(公告)日：2002-03-06

申请号：EP00830582.3

申请日：2000-08-16

Applicant: STMicroelectronics S.r.l.

Inventor： Geraci, Antonino ,  Lisi, Carlo ,  Bedarida, Lorenzo ,  Sforzin, Marco

IPC: G11C16/28 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C16/28

Abstract: A direct-comparison reading circuit for a nonvolatile memory array (2) having a plurality of memory cells (4) arranged in rows and columns (9), and at least one bit line (7), includes at least one array line (13), selectively connectable to the bit line (7), and a reference line (14); a precharging circuit (17) for precharging the array line (13) and reference line (14) at a preset precharging potential (V PC ); at least one comparator (35) having a first terminal connected to the array line (13), and a second terminal connected to the reference line (14); and an equalization circuit (15, 23, 26) for equalizing the potentials of the array line (13) and reference line (14) in the precharging step. In addition, the reading circuit includes an equalization line (15) distinct from the reference line (14); and controlled switches (23, 26) for connecting, in the precharging step, the equalization line (15) to the array line (13) and to the reference line (14), and for disconnecting the equalization line (15) from the array line (13) and from the reference line (14) at the end of the precharging step.

Abstract translation: 一种用于具有以行和列（9）排列的多个存储单元（4）和至少一个位线（7）的非易失性存储器阵列（2）的直接比较读取电路，包括至少一个阵列线（13） ），可选择地连接到位线（7）和参考线（14）; 用于以预设的预充电电位（VPC）对阵列线（13）和参考线（14）进行预充电的预充电电路（17）; 至少一个具有连接到阵列线（13）的第一端子的比较器（35）和连接到参考线（14）的第二端子; 以及用于在预充电步骤中均衡阵列线（13）和参考线（14）的电位的均衡电路（15,23,26）。 另外，读取电路包括与参考线（14）不同的均衡线（15）。 和控制开关（23,26），用于在预充电步骤中将均衡线（15）连接到阵列线（13）和参考线（14），并将均衡线（15）与阵列 在预充电步骤结束时从线（13）和参考线（14）移动。

公开(公告)号：EP1103977A1

公开(公告)日：2001-05-30

申请号：EP99830722.7

申请日：1999-11-25

Applicant: STMicroelectronics S.r.l.

Inventor： Bartoli, Simone ,  Geraci, Antonino ,  Sali, Mauro ,  Bedarida, Lorenzo

IPC: G11C7/00

CPC classification number: G11C7/1033 ,  G11C7/1045 ,  G11C7/1072

Abstract: This invention relates to a method and a corresponding circuit for reading data from an integrated electronic memory device (2) including at least one non-volatile memory matrix (4). The method comprises the following steps:

supplying the memory with an address of a memory location where a reading is to be effected;
accessing the memory matrix in a random read mode;
supplying the memory with a clock signal (CK) and an address acknowledge signal (LAN);
detecting a request for burst read mode access;
starting the burst reading as the clock signal shows a rising edge.

Abstract translation: 本发明涉及一种方法和用于从上集成电子存储器装置（2）包括至少一个非易失性存储器矩阵中读取数据的相应的电路（4）。 该方法包括以下步骤：供给所述memoryWith到的存储器位置，其中的读出将要进行的地址; 访问在一个随机读取模式的存储器矩阵; 与时钟信号（CK）供给存储器，并处理确认信号（LAN）; 检测装置，用于突发读取模式访问的请求; 开始突发读出作为时钟信号示出了上升沿。

公开(公告)号：EP1073064A1

公开(公告)日：2001-01-31

申请号：EP99830495.0

申请日：1999-07-30

Applicant: STMicroelectronics S.r.l.

Inventor： Bedarida, Lorenzo ,  Geraci, Antonino ,  Sali, Mauro ,  Bartoli, Simone

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/26

Abstract: An electrically alterable semiconductor memory comprises at least two substantially independent memory banks (1A, 1B), and first control circuit means (2, 4A, 4B) for controlling operations of electrical alteration of the content of the memory, capable of permitting the selective execution of an operation of electrical alteration of the content of one of the at least two memory banks. The memory also comprises second control circuit means (6, 4A, 4B) capable of permitting, simultaneously with said operation of electrical alteration of the content of one of the at least two memory banks, a burst mode read or page mode read operation or a standard read operation for reading the content of the other memory bank.

Abstract translation: 电可变半导体存储器包括至少两个实质独立的存储体（1A，1B），以及第一控制电路装置（2，图4A，图4B），用于控制所述存储器的内容的电改变的操作，能够允许选择性执行的 的操作的至少两个存储体中的一个的内容的电改变的。 因此，该存储器包括第二控制电路装置（6，4A，4B），其能够允许的，同时，随着所述操作的至少两个存储体中的一个的内容的电改变的，突发模式读或页面模式下读手术或 标准读取操作用于读取其它存储体的内容。

公开(公告)号：EP1071094A1

公开(公告)日：2001-01-24

申请号：EP99830403.4

申请日：1999-06-25

Applicant: STMicroelectronics S.r.l.

Inventor： Bedarida, Lorenzo ,  Dima, Vincenzo ,  Brani, Francesco ,  Defendi, Marco

IPC: G11C7/14 ,  G11C16/28

CPC classification number: G11C16/28 ,  G11C7/14

Abstract: A circuit for reading a semiconductor memory device comprises at least one global circuit (1) for generating a global reference signal (RIFN) for a respective plurality of cell-reading circuits (SA1-SAn) disposed locally in the memory device. The circuit comprises at least one circuit (51-5an) for replicating the reference signal (RIFN) locally in order to generate a local reference signal (MAT11-MAT1n) to be supplied to at least one respective cell-reading circuit (SA1-SAn).

Abstract translation: 用于读取半导体存储器件的电路包括至少一个全局电路（1），用于为本地存储在存储器件中的多个单元读取电路（SA1-SAn）生成全局参考信号（RIFN）。 该电路包括用于本地复制参考信号（RIFN）的至少一个电路（51-5an），以便产生要提供给至少一个相应的单元读取电路（SA1-SAn）的本地参考信号（MAT11-MAT1n） ）。

公开(公告)号：EP1184873B1

公开(公告)日：2008-12-10

申请号：EP00830582.3

申请日：2000-08-16

Applicant: STMicroelectronics S.r.l.

Inventor： Geraci, Antonino ,  Lisi, Carlo ,  Bedarida, Lorenzo ,  Sforzin, Marco

IPC: G11C16/28 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C16/28

公开(公告)号：EP1237279A1

公开(公告)日：2002-09-04

申请号：EP01830113.5

申请日：2001-02-21

Applicant: STMicroelectronics S.r.l.

Inventor： Bedarida, Lorenzo ,  Confalonieri, Emanuele ,  Corradi, Andrea ,  Fiorina, Sara

IPC: H03K19/003 ,  H03K19/094

CPC classification number: H03K19/00384

Abstract: Output buffer in which the switching speed of the transistors (4,5) of the output stage (1) is kept constant, independently of the variations of the supply voltage (Vcc) and of the temperature, within the acceptable operating range for the device, by controlling, as a function of the supply voltage and the operating temperature detected by a correction circuit (14), the conductivity of additional transistors (13,15) in series with the transistors (7,8) of the predriving stage (2) which drive the transistors of the output stage in conduction, the transistors being driven by an analog signal (CNTRN, CNTRP) which is generated by the correction circuit (14) and is variable with the supply voltage and the operating temperature.

Abstract translation: 输出缓冲器，其中所述输出级（1）的晶体管（4,5）的开关速度保持恒定，电源电压（Vcc）的变化的unabhängig和温度的，在可接受的工作范围为在该装置内 通过控制，作为电源电压的函数，并且通过校正电路（14）检测到的工作温度，附加晶体管（13,15）串联在预驱动级的晶体管（7,8）的电导率（2 ）你推动传导所述输出级的晶体管，该晶体管由在由所述校正电路（14）产生的，并与电源电压和工作温度变量的模拟信号（CNTRN，CNTRP）所有驱动。