公开(公告)号：EP1049100B1

公开(公告)日：2005-01-19

申请号：EP99830253.3

申请日：1999-04-28

Applicant: STMicroelectronics S.r.l.

Inventor： Bartoli, Simone ,  Sali, Mauro ,  Nava, Claudio ,  Russo, Antonio

IPC: G11C7/00 ,  G11C5/00

CPC classification number: G11C7/10 ,  G11C5/04 ,  G11C5/063 ,  G11C2207/105

公开(公告)号：EP1073063A1

公开(公告)日：2001-01-31

申请号：EP99830494.3

申请日：1999-07-30

Applicant: STMicroelectronics S.r.l.

Inventor： Bartoli, Simone ,  Bedarida, Lorenzo ,  Sali, Mauro ,  Russo, Antonio

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C16/10 ,  G11C2216/20

Abstract: An electrically alterable semiconductor memory comprises at least two memory sectors (S1-S9) the content of which is individually alterable, and first control circuit means (4, 6) for controlling operations of electrical alteration of the content of the memory, capable of permitting the selective execution of an operation of electrical alteration of the content of one of said at least two memory sectors with the possibility of suspending said execution in order to permit read access to the other of said at least two memory sectors. The memory comprises second control circuit means (8, 6) capable of permitting, during said suspension, an operation of burst mode or page mode reading of the content of the other memory sector.

Abstract translation: 电可变半导体存储器包括至少两个存储器扇区（S1-S9）的所有其是独立可变的内容，以及第一控制电路装置（4,6），用于控制所述存储器的内容的电改变的操作，能够允许的 的操作的所述一个的所述内容的电改变的至少两个存储器扇区选择性执行，以便暂停所述执行的可能性，以允许读访问另一所述的至少两个存储器扇区。 所述存储器包括第二控制电路装置能够允许，所述悬浮液期间的突发模式或其他存储器扇区的内容的页面模式读取手术的（8,6）。

公开(公告)号：EP1049100A1

公开(公告)日：2000-11-02

申请号：EP99830253.3

申请日：1999-04-28

Applicant: STMicroelectronics S.r.l.

Inventor： Bartoli, Simone ,  Sali, Mauro ,  Nava, Claudio ,  Russo, Antonio

IPC: G11C7/00 ,  G11C5/00

CPC classification number: G11C7/10 ,  G11C5/04 ,  G11C5/063 ,  G11C2207/105

Abstract: Semiconductor device comprising at least two pads (101, 102; 103, 104) for the input of external signals and/or for the output of signals from said semiconductor device, at least two uncoupling buffers (201, 202; 203, 204) each connected to each one of said pads, at least one multiplexer (10; 20) connected to said pads (101, 102; 103, 104) by means of said uncoupling buffers (201, 202; 203, 204) and at least one memory element (4; 5) suitable to generate a configuration signal (C ) operating on said multiplexer (10; 20) and said uncoupling buffers (201, 202; 203, 204) to selectively enable one or the other of said pads (101, 102; 103, 104).

Abstract translation: 半导体器件包括用于输入外部信号和/或用于从所述半导体器件输出信号的至少两个焊盘（101,102; 103,104），至少两个解耦缓冲器（201,202; 203,204） 连接到所述焊盘中的每一个，至少一个通过所述解耦缓冲器（201,202; 203,204）连接到所述焊盘（101,102; 103,104）的多路复用器（10; 20）和至少一个存储器 元件（4; 5），适于产生在所述多路复用器（10; 20）和所述非耦合缓冲器（201,202; 203,204）上操作的配置信号（C），以选择性地使得所述焊盘 102; 103，104）。