公开(公告)号：EP1073060A1

公开(公告)日：2001-01-31

申请号：EP99830483.6

申请日：1999-07-28

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Khouri, Osama ,  Sacco, Andrea ,  Picca, Massimiliano

IPC: G11C8/00

CPC classification number: G11C5/145 ,  G11C5/14 ,  G11C8/10

Abstract: The memory device (10) comprises a memory array (2) having an organisation of the type comprising global word lines (4) and local word lines (6), a global row decoder (8) addressing the global word lines (4), a local row decoder (12) addressing the local word lines (6), a global power supply stage (22) supplying the global row decoder (8), and a local power supply stage (24) supplying the local row decoder (12).

Abstract translation: 存储器件（10）包括具有包括全局字线（4）和本地字线（6）类型的组织的存储器阵列（2），寻址全局字线（4）的全局行解码器（8） 寻址本地字线（6）的本地行解码器（12），提供全局行解码器（8）的全局电源级（22）和提供本地行解码器（12）的本地电源级（24） 。

公开(公告)号：EP1073060B1

公开(公告)日：2005-09-21

申请号：EP99830483.6

申请日：1999-07-28

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Khouri, Osama ,  Sacco, Andrea ,  Picca, Massimiliano

IPC: G11C8/00

CPC classification number: G11C5/145 ,  G11C5/14 ,  G11C8/10

公开(公告)号：EP1617438B1

公开(公告)日：2006-10-25

申请号：EP04103354.9

申请日：2004-07-14

Applicant: STMicroelectronics S.r.l.

Inventor： Picca, Massimiliano ,  Zanardi, Stefano

IPC: G11C29/00

CPC classification number: G11C29/82 ,  G11C29/76

公开(公告)号：EP1617438A1

公开(公告)日：2006-01-18

申请号：EP04103354.9

申请日：2004-07-14

Applicant: STMicroelectronics S.r.l.

Inventor： Picca, Massimiliano ,  Zanardi, Stefano

IPC: G11C29/00

CPC classification number: G11C29/82 ,  G11C29/76

Abstract: An electrically programmable memory ( 100 ) including: an array ( 105 ) of a plurality of memory cells ( 210 ) arranged accordingly to a NAND architecture, said memory cells grouped into a plurality of memory blocks (225_1 - 225 K) and each memory block including a plurality of memory pages; means for receiving (106,I/O,112,115) an address corresponding to a respective memory block; selecting means ( 120,125r,195,125r,130,155 ) for selecting the addressed memory block; and means for detecting (REG_1 - REG_K,135,145,147) a failure of the addressed memory block, wherein the means for detecting a failure includes: a plurality of registers (REG_1 - REG_K), each register corresponding to a respective memory block and storing an indication (AR, RED ADD) of the failure of the respective memory block; and means for reading ( 135,145,147 ) the register corresponding to the addressed memory block in response to the receiving of the address, and wherein the programmable memory further includes at least one redundant memory block ( RED_1 - RED_M ) of memory cells including a plurality of redundant memory pages, the selecting means selecting the at least one redundant memory block in place of the addressed memory block in response to the reading of the indication of the failure.

Abstract translation: 一种电可编程存储器（100），包括：相应地配置到NAND架构的多个存储单元（210）的阵列（105），所述存储器单元分组成多个存储块（225_1-225K），每个存储块 包括多个存储器页面; 用于接收（106，I / O，112,115）与相应存储块对应的地址的装置; 选择装置（120,125r，195,125r，130,155），用于选择寻址的存储块; 以及用于检测（REG_1-REG_K，135,145,147）寻址的存储器块的故障的装置，其中用于检测故障的装置包括：多个寄存器（RE​​G_1-REG_K），每个寄存器（AR，RED ADD） 相应的存储块; 以及用于响应于所述地址的接收而读取对应于所寻址的存储器块的寄存器（135,145,147）的装置，并且其中所述可编程存储器还包括至少一个包括多个冗余的存储器单元的冗余存储器块（RED_1-RED_M） 存储器页面，所述选择装置响应于读取所述故障的指示而选择所述至少一个冗余存储器块来代替所寻址的存储器块。