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    Redundancy based NAND flash memory
    2.
    发明公开
    Redundancy based NAND flash memory 有权
    NAND Flash Speicher mit Speicherredundanz

    公开(公告)号：EP1617438A1

    公开(公告)日：2006-01-18

    申请号：EP04103354.9

    申请日：2004-07-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Picca, Massimiliano ,  Zanardi, Stefano

    IPC: G11C29/00

    CPC classification number: G11C29/82 ,  G11C29/76

    Abstract: An electrically programmable memory ( 100 ) including: an array ( 105 ) of a plurality of memory cells ( 210 ) arranged accordingly to a NAND architecture, said memory cells grouped into a plurality of memory blocks (225_1 - 225 K) and each memory block including a plurality of memory pages; means for receiving (106,I/O,112,115) an address corresponding to a respective memory block; selecting means ( 120,125r,195,125r,130,155 ) for selecting the addressed memory block; and means for detecting (REG_1 - REG_K,135,145,147) a failure of the addressed memory block, wherein the means for detecting a failure includes: a plurality of registers (REG_1 - REG_K), each register corresponding to a respective memory block and storing an indication (AR, RED ADD) of the failure of the respective memory block; and means for reading ( 135,145,147 ) the register corresponding to the addressed memory block in response to the receiving of the address, and wherein the programmable memory further includes at least one redundant memory block ( RED_1 - RED_M ) of memory cells including a plurality of redundant memory pages, the selecting means selecting the at least one redundant memory block in place of the addressed memory block in response to the reading of the indication of the failure.

    Abstract translation: 一种电可编程存储器（100），包括：相应地配置到NAND架构的多个存储单元（210）的阵列（105），所述存储器单元分组成多个存储块（225_1-225K），每个存储块 包括多个存储器页面; 用于接收（106，I / O，112,115）与相应存储块对应的地址的装置; 选择装置（120,125r，195,125r，130,155），用于选择寻址的存储块; 以及用于检测（REG_1-REG_K，135,145,147）寻址的存储器块的故障的装置，其中用于检测故障的装置包括：多个寄存器（RE​​G_1-REG_K），每个寄存器（AR，RED ADD） 相应的存储块; 以及用于响应于所述地址的接收而读取对应于所寻址的存储器块的寄存器（135,145,147）的装置，并且其中所述可编程存储器还包括至少一个包括多个冗余的存储器单元的冗余存储器块（RED_1-RED_M） 存储器页面，所述选择装置响应于读取所述故障的指示而选择所述至少一个冗余存储器块来代替所寻址的存储器块。

    An improved page buffer for a programmable memory device
    3.
    发明公开
    An improved page buffer for a programmable memory device 有权
    一种改进的可编程存储器设备的页面缓冲区

    公开(公告)号：EP1598831A1

    公开(公告)日：2005-11-23

    申请号：EP04102232.8

    申请日：2004-05-20

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Khouri, Osama ,  Zanardi, Stefano ,  Martinozzi, Giulio

    IPC: G11C16/10 ,  G11C16/26

    CPC classification number: G11C16/26

    Abstract: A page buffer ( 130 ) for an electrically programmable memory including a plurality of memory cells ( 110 ) forming a plurality of memory pages, the page buffer comprising at least one register ( 130m,130c ) for at least temporarily storing data read from or to be written into the memory cells of a selected memory page of said plurality, the at least one register comprising a plurality of latches ( 230m ), each latch being operatively associated with at least one respective signal line ( BLe,BLo,I/O-LINE ) transporting the data bit temporarily stored in the latch. A buffer element ( BUF ) is provided for decoupling an output of the latch from the respective signal line, the latch using the respective buffer element for driving the signal line according to the data bit stored therein.

    Abstract translation: 一种用于电可编程存储器的页缓冲器（130），所述电可编程存储器包括形成多个存储器页的多个存储器单元（110），所述页缓冲器包括至少一个寄存器（130m，130c），用于至少暂时存储从或者到 被写入所述多个选定存储页中的存储单元，所述至少一个寄存器包括多个锁存器（230m），每个锁存器与至少一个相应信号线（BLe，BLo，I / O- LINE）传输临时存储在锁存器中的数据位。 提供缓冲器元件（BUF），用于将锁存器的输出与相应的信号线去耦，锁存器使用相应的缓冲器元件根据存储在其中的数据位来驱动信号线。

    Memory cell integrated structure and corresponding biasing device
    4.
    发明公开
    Memory cell integrated structure and corresponding biasing device 失效
    Vorspannungsvorrichtungfürintegrierte Speicherzellenstruktur

    公开(公告)号：EP0952615A1

    公开(公告)日：1999-10-27

    申请号：EP98830238.6

    申请日：1998-04-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Zanardi, Stefano ,  Branchetti, Maurizio ,  Ghezzi, Stefano

    IPC: H01L27/115 ,  G05F3/20

    CPC classification number: H01L27/115 ,  G05F3/205

    Abstract: The invention relates to an integrated structure (1) for memory cells formed over a semiconductor substrate (2) doped with a first dopant type and including at least one memory cell (CM) in turn formed in a conductive well (3) provided in said semiconductor substrate (2) and doped with a second dopant type, said conductive well (3) having an additional well (4) formed therein which is doped with the first dopant type and comprises active areas (5,6) of the memory cell (CM).
    According to the invention, a substrate bias terminal (8), formed in the additional well (4), is further associated with the memory cell (CM) to receive a suitable bias voltage (Vpol) to lower the threshold voltage (Vth) of the memory cell (CM) by body effect.
    The invention also relates to a biasing device (13) for a memory cell (CM) which has at least one substrate bias terminal (8) associated therewith, the biasing device comprising at least a first sub-threshold circuitry block (A) adapted to supply an appropriate current during the device standby phase through a restore transistor (M1) connected between a supply voltage reference (Vcc) and the substrate bias terminal (8) of the memory cell (CM), and having a control terminal connected to a bias circuit (14), in turn connected between the supply voltage reference (Vcc) and a ground voltage reference (GND) to drive the restore transistor (M1) with a current of limited value.
    The device according to the invention further comprises a second feedback block (B) for fast charging the substrate bias terminal (8), being connected between the supply voltage reference (Vcc) and the ground voltage reference (GND) and comprising a first bias transistor (M2) having a control terminal connected to the ground voltage reference (GND) via a stabilization transistor (M3), having in turn a control terminal connected to an output node (OC), and to the control terminal of a first regulation transistor (M4) connected between the supply voltage reference (Vcc) and the ground voltage reference (GND), the stabilization transistor (M3) and first regulation transistor (M4) providing feedback for the bias transistor (M2), thereby to restrict the voltage range of the output node (OC).

    Abstract translation: 本发明涉及一种用于存储单元的集成结构（1），其形成于掺杂有第一掺杂剂类型的半导体衬底（2）上，并且还包括至少一个存储单元（CM），所述至少一个存储单元又形成在所述导电阱 半导体衬底（2）并掺杂有第二掺杂剂类型，所述导电阱（3）具有形成在其中的附加阱（4），其中掺杂有第一掺杂剂类型，并且包括存储器单元的有源区（5,6） 厘米）。 根据本发明，形成在附加阱（4）中的衬底偏置端子（8）还与存储单元（CM）相关联以接收合适的偏置电压（Vpol）以降低阈值电压（Vth） 记忆体（CM）通过身体效应。 本发明还涉及一种用于存储单元（CM）的偏置装置（13），其具有至少一个与其相关联的衬底偏置端子（8），所述偏置装置至少包括第一子阈值电路块（A） 在器件待机阶段通过连接在电源电压基准（Vcc）和存储单元（CM）的衬底偏置端子（8）之间的还原晶体管（M1）提供适当的电流，并且具有连接到偏置的控制端子 电路（14）又连接在电源电压基准（Vcc）和接地电压基准（GND）之间，以限制电流驱动恢复晶体管（M1）。 根据本发明的装置还包括用于对衬底偏置端子（8）进行快速充电的第二反馈块（B），其连接在电源电压参考（Vcc）和接地电压基准（GND）之间，并且包括第一偏置晶体管 （M2），其具有经由稳定晶体管（M3）连接到接地电压基准（GND）的控制端子，其具有连接到输出节点（OC）的控制端子和第一调节晶体管（...的控制端子） M4）连接在电源电压基准（Vcc）和接地电压基准（GND）之间，稳定晶体管（M3）和第一调节晶体管（M4）为偏置晶体管（M2）提供反馈，从而限制 输出节点（OC）。

    An improved page buffer for a programmable memory device
    5.
    发明公开
    An improved page buffer for a programmable memory device 有权
    Verbesserter Seitenspeicherfüreine programmierbare Speichervorrichtung

    公开(公告)号：EP1610343A1

    公开(公告)日：2005-12-28

    申请号：EP04102942.2

    申请日：2004-06-24

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Zanardi, Stefano ,  Martinozzi, Giulio

    IPC: G11C16/10 ,  G11C16/26

    CPC classification number: G11C16/26 ,  G11C16/10 ,  G11C2216/14

    Abstract: A page buffer ( 130 ) for an electrically programmable memory ( 100 ) including a plurality of memory cells ( 110 ) forming a plurality of memory pages, the page buffer comprising a plurality of storage units ( 205 ) for at least temporarily storing data read from or to be written into the memory cells of selected memory pages of said plurality, each storage unit comprising a first latch ( 230-1 ) and a second latch ( 230-2 ), operatively associated with a selected bit line ( BLe,BLo ) of memory cells, for reading/programming the data bit from/into a selected memory cell belonging to said bit line, and with a respective data line ( I/O-LINE ), for transporting the data bit read from a selected memory cell to an output interface ( 140,I/O ) of the memory, in which each of said first and second latches in the storage unit includes: a first input/output terminal ( 237-1a,237-2a ) and a second input/output terminal ( 237-1b,237-2b ); input switching means ( 280-1a,280-1b,280-2a,280-2b ) for loading into the latch the data bit to be written and to be temporarily stored in response to an input control signal ( DI-1,DI-2 ) corresponding to the data bit, the input switching means having an input terminal connected to the respective data line for receiving a set voltage provided therethrough, a first output terminal coupled to the first input/output terminal of the latch and a second output terminal coupled to the second input/output terminal, and a control terminal receiving the input control signal, the input switching means providing the set voltage to the first or second input/output terminal of the latch depending on the data bit to be written; and an output switch device ( 280-1b,280-2b ) for transferring onto the respective data line the read data bit temporarily stored into the latch in response to an output control signal ( DO-1,DO-2 ), the output switch device having a first terminal coupled to one among the first and second input/output terminals of the latch, a second terminal connected to the respective data line and a control terminal receiving the output control signal.

    Abstract translation: 一种用于电可编程存储器（100）的页缓冲器（130），包括形成多个存储器页的多个存储器单元（110），所述页缓冲器包括多个存储单元（205），用于至少临时存储从 或被写入所述多个选定存储器页的存储单元中，每个存储单元包括与所选位线（BLe，BLo）可操作地相关联的第一锁存器（230-1）和第二锁存器（230-2） 的存储单元，用于从属于所述位线的所选择的存储单元中的数据位读取/编程数据位，以及相应的数据线（I / O-LINE），用于将从选择的存储单元读取的数据位传送到 存储器的输出接口（140，I / O），其中存储单元中的每个所述第一和第二锁存器包括：第一输入/输出端子（237-1a，237-2a）和第二输入/输出 端子（237-1b，237-2b）; 输入切换装置（280-1a，280-1b，280-2a，280-2b），用于响应于输入控制信号（DI-1，DI-1）将要写入的数据位加载到锁存器中并临时存储， 2），输入切换装置具有连接到相应数据线的输入端，用于接收通过其提供的设定电压，耦合到锁存器的第一输入/输出端的第一输出端和第二输出端 耦合到所述第二输入/输出端子，以及控制端子，接收所述输入控制信号，所述输入开关装置根据要写入的数据位向所述锁存器的所述第一或第二输入/输出端提供所述设定电压; 以及用于响应于输出控制信号（DO-1，DO-2）将临时存储到锁存器中的读取数据位传送到相应数据线的输出开关装置（280-1b，280-2b），输出开关 装置，其具有耦合到锁存器的第一和第二输入/输出端子中的一个的第一端子，连接到相应数据线的第二端子和接收输出控制信号的控制端子。

    A Programmable memory device with an improved redundancy structure
    7.
    发明公开
    A Programmable memory device with an improved redundancy structure 审中-公开
    Ein programmierbarer Speicher mit verbesserter Redundanz-Struktur

    公开(公告)号：EP1624463A1

    公开(公告)日：2006-02-08

    申请号：EP04103353.1

    申请日：2004-07-14

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Zanardi, Stefano

    IPC: G11C29/00

    CPC classification number: G11C29/846

    Abstract: An electrically programmable memory device ( 100 ) is proposed including: a matrix of memory cells ( 210 ) arranged in a plurality ( 106 ) of memory arrays and at least one redundancy array ( 107 ); and means ( 150,155,160,165 ) for substituting the use of each memory array with the use of one of the at least one redundancy array in response to a failure of the memory array, wherein the memory arrays are partitioned into at least one set, the means for substituting including: means ( 165 ) for associating each set with a predetermined one of the at least one redundancy array; a flag ( F1 - FK ) for each memory array indicative of the failure of the memory array; and selecting means ( SW,SW_red ) for enabling each memory array or the associated redundancy array according to the corresponding flag.

    Abstract translation: 提出一种电可编程存储器件（100），包括：布置在多个（106）存储器阵列中的存储器单元（210）矩阵和至少一个冗余阵列（107）; 以及用于响应于所述存储器阵列的故障而使用所述至少一个冗余阵列中的一个来代替使用每个存储器阵列的装置（150,155,160,165），其中所述存储器阵列被划分为至少一个组，所述装置 替换包括：用于将每个集合与所述至少一个冗余阵列中的预定的一个相关联的装置（165） 用于指示存储器阵列的故障的每个存储器阵列的标志（F1-FK）; 和选择装置（SW，SW_red），用于根据相应的标志启用每个存储器阵列或相关的冗余阵列。

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