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    Single supply voltage nonvolatile memory device with hierarchical row decoding
    1.
    发明公开
    Single supply voltage nonvolatile memory device with hierarchical row decoding 有权
    Einzige SpeisespannungsschaltungfürnichtflüchtigenSpeicher mit hierarchicalischem Reihendekodierer

    公开(公告)号：EP1073060A1

    公开(公告)日：2001-01-31

    申请号：EP99830483.6

    申请日：1999-07-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Khouri, Osama ,  Sacco, Andrea ,  Picca, Massimiliano

    IPC: G11C8/00

    CPC classification number: G11C5/145 ,  G11C5/14 ,  G11C8/10

    Abstract: The memory device (10) comprises a memory array (2) having an organisation of the type comprising global word lines (4) and local word lines (6), a global row decoder (8) addressing the global word lines (4), a local row decoder (12) addressing the local word lines (6), a global power supply stage (22) supplying the global row decoder (8), and a local power supply stage (24) supplying the local row decoder (12).

    Abstract translation: 存储器件（10）包括具有包括全局字线（4）和本地字线（6）类型的组织的存储器阵列（2），寻址全局字线（4）的全局行解码器（8） 寻址本地字线（6）的本地行解码器（12），提供全局行解码器（8）的全局电源级（22）和提供本地行解码器（12）的本地电源级（24） 。

    Non volatile memory with detection of short circuits between word lines
    2.
    发明授权
    Non volatile memory with detection of short circuits between word lines 有权
    非易失性存储器与检测的字线之间的短路的

    公开(公告)号：EP1083575B1

    公开(公告)日：2007-11-14

    申请号：EP99830567.6

    申请日：1999-09-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Sacco, Andrea ,  Mognoni, Sabina

    IPC: G11C29/00

    CPC classification number: G11C29/50 ,  G01R31/3004 ,  G11C29/02

    Abstract: The non volatile memory device integrates, in one and the same chip (100), the array (2) of memory cells, a voltage regulator (REG) which supplies a regulated operating voltage (Vr) to a selected word line (LWL1), and a short circuit detecting circuit (10). The short circuit detecting circuit detects the output voltage (IM1) of the voltage regulator (REG), which is correlated to the current (Iw) for biasing the cells (3) of the word line selected (LWL1). Once settled to the steady state condition, the output current (IM1) assumes one first value (IM1') in the absence of short circuits, and one second value (IM1") in the presence of a short circuit between the word line selected (LWL1) and one or more adjacent word lines (LWL0, LWL2, ..., LWLn). The short circuit detecting circuit (10) compares the output current (IM1) of the voltage regulator (REG) with a reference value (Iref) and generates at output a short circuit digital signal (Vo) which indicates the presence or otherwise of a short circuit.

    Method of regulating the voltages on the drain and body terminals of a nonvolatile memory cell during programming and corresponding programming circuit
    5.
    发明公开
    Method of regulating the voltages on the drain and body terminals of a nonvolatile memory cell during programming and corresponding programming circuit 审中-公开
    用于控制所述漏极的电压和一个非易失性存储器单元的编程时的基板和相应的编程电路的方法

    公开(公告)号：EP1331645A2

    公开(公告)日：2003-07-30

    申请号：EP02029092.0

    申请日：2002-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Mognoni, Sabina ,  Motta, Ilaria ,  Sacco, Andrea

    IPC: G11C16/30

    CPC classification number: G11C16/30

    Abstract: The invention relates to a method and a programming circuit for the regulation of voltages on the drain (D) and body (B) terminals of a non-volatile memory cell (3) while being programmed. These voltages are applied through a programming circuit (1) inserted on a conduction pattern that transfers a predetermined voltage value (VPD,Vb) on at least one terminal (D,B) of the memory cell. The method comprises a local regulation phase of said voltage value, within the programming circuit, for deleting the effect of a parasitic resistor (R par ) lying on the conduction pattern.

    Abstract translation: 本发明涉及一种方法和一种编程电路，用于电压在漏极（D）和体（B）的调节中的非易失性存储单元（3）而被编程的端子。 （1）插入这些电压通过一个编程电路施加在传导图案做传输预定的电压值（VPD，Vb）中的至少一个端子上（D，B）的存储单元的。 该方法包括将所述电压值的本地调节阶段，编程电路内，用于删除一个寄生电阻器（R PAR）的影响躺在传导图案。

    Non volatile memory with detection of short circuits between word lines
    6.
    发明公开
    Non volatile memory with detection of short circuits between word lines 有权
    非易失性存储器与检测的字线之间的短路的

    公开(公告)号：EP1083575A1

    公开(公告)日：2001-03-14

    申请号：EP99830567.6

    申请日：1999-09-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Sacco, Andrea ,  Mognoni, Sabina

    IPC: G11C29/00

    CPC classification number: G11C29/50 ,  G01R31/3004 ,  G11C29/02

    Abstract: The non volatile memory device integrates, in one and the same chip (100), the array (2) of memory cells, a voltage regulator (REG) which supplies a regulated operating voltage (Vr) to a selected word line (LWL1), and a short circuit detecting circuit (10). The short circuit detecting circuit detects the output voltage (IM1) of the voltage regulator (REG), which is correlated to the current (Iw) for biasing the cells (3) of the word line selected (LWL1). Once settled to the steady state condition, the output current (IM1) assumes one first value (IM1') in the absence of short circuits, and one second value (IM1") in the presence of a short circuit between the word line selected (LWL1) and one or more adjacent word lines (LWL0, LWL2, ..., LWLn). The short circuit detecting circuit (10) compares the output current (IM1) of the voltage regulator (REG) with a reference value (Iref) and generates at output a short circuit digital signal (Vo) which indicates the presence or otherwise of a short circuit.

    Abstract translation: 所述非易失性存储装置在一个和相同的芯片（100）集成，所述阵列的存储器单元（2），一个电压调节器（REG），其向所选择的字线经调节的工作电压（VR）供给（FO1） 以及短路检测电路（10）。 短路检测电路，用于偏置所述细胞检测其相关的电流（IW）的电压调节器（REG），所有的输出电压（IM1）（3）（FO1）选择的字线的。 一旦稳定到稳态条件时，输出电流（IM1）übernimmt一个firstValue（IM1“）在不存在短路，并且一个第二值​​（IM1“）（在字线之间的短路的选择存在 FOC1）和一个或多个相邻的字线（LWL 0，FO2，...，LWLn），该短路检测电路（10）比较所述电压调节器（REG）与参考值的输出电流（IM1）（I REF） 并在输出短路数字信号（VO），其指示存在或以其它方式的短路的基因率。

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