TIMING SYSTEM INCLUDING A MASTER DEVICE AND AT LEAST A SLAVE DEVICE SYNCHRONIZED WITH EACH OTHER AND RELATED SYNCHRONIZATION METHOD

    公开(公告)号:EP4113244A1

    公开(公告)日:2023-01-04

    申请号:EP22179366.4

    申请日:2022-06-16

    Abstract: System including a master device (2) including: a master oscillator (21,22) generating a first clock signal (MAIN_CLK_MASTER); a master timing stage (23) which implements a master counter (99) dependent on the first clock signal and generates a first local signal (TIMEBASE_MASTER) dependent on the master counter; and a master synchronization stage (24) which generates a synchronization signal (CLKSW) synchronous with the first local signal. The system further includes a slave device (4) including: a slave oscillator (41,42) generating a second clock signal (MAIN_CLK_SLAVE) frequency-locked with the first clock signal; a slave timing stage (43) which implements a slave counter (199) dependent on the second clock signal and generates a second local signal (TIMEBASE_SLAVE) dependent on the slave counter; and a slave synchronization stage (44,45) which reads, with a timing that depends on the synchronization signal, the value of the slave counter, compares the read value with an expected value and tunes the value of the slave counter according to the outcome of the comparison.

    SYSTEM BASIS CHIP, CORRESPONDING PROCESSING SYSTEM, DEVICE AND METHOD

    公开(公告)号:EP4156428A1

    公开(公告)日:2023-03-29

    申请号:EP22192315.4

    申请日:2022-08-26

    Abstract: A system basis chip (30a) is described. The system basis chip (30a) comprises a power supply circuit (300a) configured to receive an input voltage (V in ) and generate a plurality of voltages (V pre , V core , V I/O , V ext , V 1 , V 2 , V 3 ), and a control circuit (40).
    Specifically, the power supply circuit (300a) is configured to selectively switch on a first (Va) and a second (Vb) voltage of the voltages (V pre , V core , V I/O , V ext , V 1 , V 2 , V 3 ) as a function of a control signal (CTRL). The control circuit (40) measures a resistance value of an external resistor (R set ) connected to a terminal (340) and selects one of a plurality of configurations as a function of the measured resistance value, wherein a first configuration (CFG1) indicates that said first voltage (Va) should be switched on before said second voltage (Vb) and a second configuration (CFG2) indicates that said second voltage (Vb) should be switched on before said first voltage (Va). Accordingly, the control circuit (40) may generate the control signal (CTRL) in order to switch on in sequence the first (Va) and the second (Vb) voltage according to the selected configuration (CODE).

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