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公开(公告)号：EP3648349A1
公开(公告)日：2020-05-06
申请号：EP19203837.0
申请日：2019-10-17
Applicant: STMicroelectronics S.r.l.
Inventor： POLETTO, Vanni , ALAGNA, Diego , ERRICO, Nicola , CIGNOLI, Marco , DE AGOSTINI, Gian Battista
Abstract: A PWM signal generator (12) configured (D) to provide a supply current (I LOAD ) to an electrical load (L) generates PWM signals at a first frequency (f PWM ), the PWM signals having a duty cycle.
Operating the generator involves:
- receiving a set point signal (SP) indicative of a target average value for the supply current (I LOAD ),
- sensing (20) a sensing signal indicative of a current actual value of the supply current (I LOAD ),
- performing a closed-loop control of the supply current (I LOAD ) targeting the target value (SP) for the supply current via a controller (14; 141, 142, 143, 144) such as a PID Controller which controls (PID) the duty cycle of the PWM signals generated by the PWM signal generator (12) as a function of the offset (18) of the sensing signal with respect to the set point signal (SP).-
公开(公告)号：EP4134688A2
公开(公告)日：2023-02-15
申请号：EP22186502.5
申请日：2022-07-22
Applicant: STMicroelectronics S.r.l.
Inventor： ERRICO, Nicola , BENDOTTI, Valerio , FINAZZI, Luca , BAGNATI, Gaudenzia
Abstract: A circuit, comprising: a high-side transistor pair (S 0H , HS) and a low-side transistor pair (S 0L , LS) having a common intermediate node (OUT S, OUT), wherein the high-side transistor pair (S 0H , HS) comprises a first transistor (HS) having a control node and a current flowpath therethrough configured to provide a current flow line between a supply voltage node (OUT_D) and the intermediate node (OUT_S, OUT) as well as a second transistor (S 0H ) having a current flowpath therethrough coupled to the control node of the first transistor (HS), wherein the low-side transistor pair (S 0L , LS) comprises a third transistor (LS) having a control node and a current flowpath therethrough configured to provide a current flow line between the intermediate node (OUT, OUT_S) and the reference voltage node (PGND) as well as a fourth transistor (S 0L ) having a current flowpath therethrough coupled to the control node of the third transistor (LS). The circuit comprises testing circuitry (40; 50) comprising a test-mode node (TM) configured to receive a test-mode signal (V TM ), the testing circuitry (40; 50) configured to be coupled to at least one of the second transistor (S 0H ) in the high-side transistor pair (S 0H , HS) and of the fourth transistor (S 0L ) in the low-side transistor pair (S 0L , LS) to apply thereto the test-mode signal (V TM ) wherein the at least one of the high-side transistor pair (S 0H , HS) and the low-side transistor pair (S 0L , LS) is made selectively conductive or non-conductive based on the test-mode signal (V TM ).
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公开(公告)号：EP4156428A1
公开(公告)日：2023-03-29
申请号：EP22192315.4
申请日：2022-08-26
Applicant: STMicroelectronics S.r.l.
Inventor： SOLE, Luigi , GAUDIANO, Rossella , CANTARINI, Marta , ERRICO, Nicola , GIORDANO, Antonio
IPC: H02J1/08
Abstract: A system basis chip (30a) is described. The system basis chip (30a) comprises a power supply circuit (300a) configured to receive an input voltage (V in ) and generate a plurality of voltages (V pre , V core , V I/O , V ext , V 1 , V 2 , V 3 ), and a control circuit (40).
Specifically, the power supply circuit (300a) is configured to selectively switch on a first (Va) and a second (Vb) voltage of the voltages (V pre , V core , V I/O , V ext , V 1 , V 2 , V 3 ) as a function of a control signal (CTRL). The control circuit (40) measures a resistance value of an external resistor (R set ) connected to a terminal (340) and selects one of a plurality of configurations as a function of the measured resistance value, wherein a first configuration (CFG1) indicates that said first voltage (Va) should be switched on before said second voltage (Vb) and a second configuration (CFG2) indicates that said second voltage (Vb) should be switched on before said first voltage (Va). Accordingly, the control circuit (40) may generate the control signal (CTRL) in order to switch on in sequence the first (Va) and the second (Vb) voltage according to the selected configuration (CODE).-
公开(公告)号：EP3926348A1
公开(公告)日：2021-12-22
申请号：EP21178626.4
申请日：2021-06-09
Applicant: STMicroelectronics S.r.l.
Inventor： POLETTO, Vanni , ERRICO, Nicola , VILMERCATI, Paolo , CIGNOLI, Marco , GENNA, Vincenzo Salvatore , ALAGNA, Diego
IPC: G01R19/00 , G01R19/165 , H02M1/00
Abstract: A circuit (100') comprises a high-side switch (HS) and a low-side switch (LS) arranged between a supply node (D) and a reference node (G), the high-side and low-side switches having an intermediate node (Q). A switching control signal ( com ) is applied with opposite polarities to the high-side and low-side switches. An inductive load (L) is coupled between the intermediate node (Q) and one of said supply node (D) and said reference node (G).
The circuit (100') further comprises current sensing circuitry (CS') configured to:
sample (12a, 14a) a first value ( I a ) of the load current flowing in one of the high-side and low-side switches at a first sampling instant ( t 1 ) before a commutation ( t s ) of the switching control signal ( com ),
sample (12b, 14b) a second value ( I b ) of the load current flowing in the other of the high-side and low-side switches at a second sampling instant ( t 2 ) after said commutation ( t s ) of said switching control signal ( com ),
sample (12b, 14c) a third value ( I c ) of the load current flowing in the other of the high-side and low-side switches at a third sampling instant ( t 3 ) after said second sampling instant ( t 2 ), and
generate (18) a failure signal ( fail ) as a function of said first ( I a ), second ( I b ) and third ( I c ) sampled values of the load current.-
公开(公告)号：EP4372396A1
公开(公告)日：2024-05-22
申请号：EP23206339.6
申请日：2023-10-27
Applicant: STMicroelectronics S.r.l.
Inventor： ERRICO, Nicola , CANNONE, Alessandro , FERRARA, Enrico , PISCITELLI, Luigi
CPC classification number: G01R31/2829 , G05B9/03
Abstract: A circuit includes: first analog-to-digital converters, ADCs (105) configured to be coupled to respective ones of first sensors(101); a first multiplexer, MUX (111) coupled to output terminals of the first ADCs; a second MUX (109) configured to be coupled to second sensors (103) which are redundant sensors for the first sensors; a second ADC (107) coupled to an output terminal of the second MUX, the first MUX and the second MUX being controlled by a selection signal (108); a first checker circuit (133) configured to compare a first data at an output terminal of the first MUX with a second data at an output terminal of the second ADC; and a plurality of switches (155) coupled between respective ones of the input terminals of the second MUX and a reference voltage node(154).
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Patent Agency Ranking
公开(公告)号：EP4134688A3
公开(公告)日：2023-03-01
申请号：EP22186502.5
申请日：2022-07-22
Applicant: STMicroelectronics S.r.l.
Inventor： ERRICO, Nicola , BENDOTTI, Valerio , FINAZZI, Luca , BAGNATI, Gaudenzia
Abstract: A circuit, comprising: a high-side transistor pair (S 0H , HS) and a low-side transistor pair (S 0L , LS) having a common intermediate node (OUT S, OUT), wherein the high-side transistor pair (S 0H , HS) comprises a first transistor (HS) having a control node and a current flowpath therethrough configured to provide a current flow line between a supply voltage node (OUT_D) and the intermediate node (OUT_S, OUT) as well as a second transistor (S 0H ) having a current flowpath therethrough coupled to the control node of the first transistor (HS), wherein the low-side transistor pair (S 0L , LS) comprises a third transistor (LS) having a control node and a current flowpath therethrough configured to provide a current flow line between the intermediate node (OUT, OUT_S) and the reference voltage node (PGND) as well as a fourth transistor (S 0L ) having a current flowpath therethrough coupled to the control node of the third transistor (LS). The circuit comprises testing circuitry (40; 50) comprising a test-mode node (TM) configured to receive a test-mode signal (V TM ), the testing circuitry (40; 50) configured to be coupled to at least one of the second transistor (S 0H ) in the high-side transistor pair (S 0H , HS) and of the fourth transistor (S 0L ) in the low-side transistor pair (S 0L , LS) to apply thereto the test-mode signal (V TM ) wherein the at least one of the high-side transistor pair (S 0H , HS) and the low-side transistor pair (S 0L , LS) is made selectively conductive or non-conductive based on the test-mode signal (V TM ).
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7.发明公开
公开(公告)号：EP4160350A1
公开(公告)日：2023-04-05
申请号：EP22192568.8
申请日：2022-08-29
Applicant: STMicroelectronics S.r.l.
Inventor： CIGNOLI, Marco , ERRICO, Nicola , VILMERCATI, Paolo , CASTORINA, Stefano , FERRARA, Enrico
IPC: G05F1/56 , H03K19/007
Abstract: Disclosed herein is a single integrated circuit chip with a main logic (11) that operates a vehicle component such as a valve driver. Isolated from the main logic (11) within the chip is a safety area (12') that operates to verify proper operation of the main logic. The safety area (12') is internally powered by an internal regulated voltage (VREG) generated by an internal voltage regulator that generates the internal regulated voltage from an external voltage (PWR_IN) while protecting against shorts of the external line delivering the external voltage. The safety area (12') includes protection circuits (25) that level shift external analog signals downward in voltage for monitoring within the safety area, the protection circuits (25) serving to protect against shorts of the external line delivering the external analog signals.
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公开(公告)号：EP4145150A1
公开(公告)日：2023-03-08
申请号：EP22189096.5
申请日：2022-08-05
Applicant: STMicroelectronics S.r.l.
Inventor： CANNONE, Alessandro , FERRARA, Enrico , ERRICO, Nicola , DONZELLI, Gea
IPC: G01R31/3167 , G01R31/00 , G01R31/317 , G06F30/30 , B60W30/00
Abstract: Disclosed herein is a single integrated circuit chip including main logic (11) that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area (12') that operates to verify proper operation of the main logic (11). A checker circuit (16') within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit (16') receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.
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公开(公告)号：EP4012865A1
公开(公告)日：2022-06-15
申请号：EP21209605.1
申请日：2021-11-22
Applicant: STMicroelectronics S.r.l.
Inventor： ERRICO, Nicola , GIORDANO, Antonio , PENNISI, Orazio , PEDONE, Leonardo , FINAZZI, Luca
IPC: H02H3/087
Abstract: An overcurrent (OVC) diagnostic circuit comprises comparator circuitry (200) configured to sense a current through a load (L) and compare the intensity of the current sensed with a comparison threshold which can be set to a first, lower threshold value (OVC_thr_1) and to a second, higher threshold value (OVC_thr_2). Logic circuitry (300) receives from the comparator circuitry (200) a comparison signal having a first value or a second value as a function of whether the current intensity is lower or higher than the comparison threshold (OVC_thr_1, OVC_thr_2). The logic circuitry (300) is configured (302) to set the comparison threshold of the comparator circuitry (200) alternately to the first threshold value (OVC_thr_1) and to the second threshold value (OVC_thr_2) and:
assert a first overcurrent event signal (OVC_1_Fault) in response to the comparison signal having the second value with the comparison threshold set to the first threshold value (OVC_thr_1) and the first value with the comparison threshold set to the second threshold value (OVC_thr_2),
assert a second overcurrent event signal (OVC_2_Fault) in response to the comparison signal having the second value both with the comparison threshold set to the first threshold value (OVC_thr_1) and with the comparison threshold set to the second threshold value (OVC_thr_2).-
公开(公告)号：EP3996281A1
公开(公告)日：2022-05-11
申请号：EP21204292.3
申请日：2021-10-22
Applicant: STMicroelectronics S.r.l.
Inventor： ERRICO, Nicola , ANNOVAZZI, Marzia , CANNONE, Alessandro , FERRARA, Enrico , DONZELLI, Gea , TURBANTI, Paolo
Abstract: A circuit (100) for use in transmission control units and braking control units for motor vehicles comprises of plurality of N sensing channels such as BJT-based temperature sensing channels. Each channel includes a first main sensing node (S_CH_1 to S_CH_N) and a second redundancy sensing node (S_CH_1R to S_CH_NR) paired therewith. A plurality of N analog-to-digital converters (ADC_1 to ADC_N) are coupled to the first sensing nodes (S_CF_1 to S_CH_N), with digital processing circuitry (101, 102) coupled to the converters (ADC 1 to ADC N) and configured to perform, e.g. interpolator processing of the N first digital signals. A pair of multiplexers (MUX1, MUX2) are coupled to the second sensing nodes (S_CF_1R to S_CF_NR) and to the N analog-to-digital converters (ADC_1 to ADC_N), with a further analog-to-digital converter (ADC_R) coupled to the output of the second multiplexer (MUX2). Error checking circuitry (103) is coupled to the outputs of the second multiplexer (MUX2) and the further analog-to-digital converter (ADC_R) to compare, at each time window in the sequence of N time windows, a first digital value (TEMP _CODE) and a second digital value (TEMP_CODE_RED) resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes (S_CF_1 to S_CH_N), and an analog sensing signal at the second sensing paired with the selected one of the first sensing nodes (S_CF_1 to S_CH_N).
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