公开(公告)号：EP0650254B1

公开(公告)日：1998-09-30

申请号：EP94830380.5

申请日：1994-07-25

Applicant: STMicroelectronics S.r.l.

Inventor： Fagnani, Mauro ,  Ferrario, Bruno ,  Sandri, Paolo

IPC: H03F1/30

CPC classification number: H03F1/305

公开(公告)号：EP0709948B1

公开(公告)日：2002-08-21

申请号：EP94830507.3

申请日：1994-10-27

Applicant: STMicroelectronics S.r.l.

Inventor： Sandri, Paolo ,  Borghi, Maria Rosa ,  Rigazio, Luca

IPC: H02M3/00 ,  H02M3/156

CPC classification number: H02M3/156 ,  H02M2001/0032 ,  Y02B70/16

公开(公告)号：EP0650249B1

公开(公告)日：1999-10-13

申请号：EP94830381.3

申请日：1994-07-25

Applicant: STMicroelectronics S.r.l.

Inventor： Borghi, Maria Rosa ,  Sandri, Paolo

IPC: H02M3/156 ,  G05F1/575

CPC classification number: G05F1/575 ,  H02M3/156 ,  H02M3/1563 ,  H02M2001/0032 ,  Y02B70/16

公开(公告)号：EP1128391A1

公开(公告)日：2001-08-29

申请号：EP00830124.4

申请日：2000-02-22

Applicant: STMicroelectronics S.r.l.

Inventor： Camera, Alessandro ,  Sandri, Paolo ,  Bellomo, Ignazio ,  Pidutti, Albino

IPC: G11C29/00

CPC classification number: G11C29/50004 ,  G06F2201/81 ,  G11C16/04 ,  G11C29/50

Abstract: A method of testing an integrated circuit (1; 100) comprising a programmable, non-volatile memory with a matrix (2; 20) of memory cells comprises a step of programming substantially all of the memory cells of the matrix (2; 20), and a step of accessing the programmed memory cells in order to identify the lowest threshold voltage of the programmed cells, the latter step providing for the addressing, in succession, of all of the locations of the memory of which the memory cells have been programmed and, for each location addressed: a) the supply of an initial selection voltage definitely lower than the lowest threshold voltage to a line (WL; WL1-WL8) of the matrix (2; 20) corresponding to the location currently addressed, b) a reading of the cells of the location currently addressed with the use of reading circuits (SA; 21) of the memory, c) repetition of step b), progressively increasing the selection voltage supplied to the line (WL; WL1-WL8) of the matrix (2; 20) corresponding to the location currently addressed until it is detected that at least one of the bits of the location currently addressed has switched, the selection voltage for which the switching is detected being the lowest threshold voltage, d) comparison of the lowest threshold voltage of the location currently addressed with a stored value corresponding to the lowest of the lowest threshold voltages of the locations previously addressed, and e) storage of the lowest threshold voltage of the location currently addressed if it is lower than the stored value.

Abstract translation: 集成电路的测试方法，（1; 100）;存储器单元基本上包括编程的步骤中的所有矩阵的存储器单元（2; 20），包括一个可编程的，非易失性存储器与基质（20 2） 和访问编程的存储器单元，以便识别所述编程的单元的最低阈值电压的步骤中，将后一步骤提供用于寻址，连续，所有这些存储器的位置中的存储器单元已经被编程 并且，对于寻址每个位置：a）一个初始选择电压肯定高于最低阈值电压低的到线（WL的供应;所述基质（2 WL1-WL8）;当前被寻址的对应于所述位置20），b）中 （SA; 21）的位置的单元的读出当前与使用读取电路的寻址的存储器中，c）将步骤b的重复）逐步增加提供给线（WL选择电压;的WL1-WL8） 所述基质（2; 20）到相应的 当前被寻址，直到检测到它的位置没有当前被寻址的位置的比特中的至少一个已切换，对于其中检测为最低的阈值电压的切换选择电压，d）中的位置的最低阈值电压的比较当前被寻址的 与存储的值对应于最低此前讨论过的位置的最低阈值电压的，以及e）如果它小于所存储的值的情况下，当前被寻址的位置的最低阈值电压的存储。

公开(公告)号：EP1104935A1

公开(公告)日：2001-06-06

申请号：EP99830746.6

申请日：1999-12-01

Applicant: STMicroelectronics S.r.l.

Inventor： Camera, Alessandro ,  Sandri, Paolo ,  Bellomo, Ignazio ,  Marino, Filippo

IPC: H01L21/66

CPC classification number: H01L22/22

Abstract: An integrated device (100) comprises at least one circuit element (Rp) and a plurality of trimming elements (Rti) which can be connected selectively to the at least one circuit element (Rp) in order to achieve a predetermined tolerance of a characteristic parameter of the at least one circuit element (Rp); the integrated device (100) includes a plurality of electronic switches (Mi), each of which can be switched between a first state and a second state in which it activates and deactivates a corresponding one of the trimming elements (Rti), respectively, and means (120) for storing an indication of the states of the electronic switches (Mi) and for operating each electronic switch (Mi) in the first state or in the second state according to the indication stored.

Abstract translation: 集成装置（100）包括至少一个电路元件（Rp）和多个修整元件（Rti），可以选择性地连接到至少一个电路元件（Rp），以便实现特性参数的预定公差 的所述至少一个电路元件（Rp）; 集成装置（100）包括多个电子开关（Mi），每个电子开关可以在第一状态和第二状态之间切换，在第一状态和第二状态之间分别激活和去激活对应的修剪元件（Rti），以及 用于根据存储的指示存储电子开关（Mi）的状态的指示和用于在第一状态或第二状态下操作每个电子开关（Mi）的装置（120）。