Abstract:
A method of testing an integrated circuit (1; 100) comprising a programmable, non-volatile memory with a matrix (2; 20) of memory cells comprises a step of programming substantially all of the memory cells of the matrix (2; 20), and a step of accessing the programmed memory cells in order to identify the lowest threshold voltage of the programmed cells, the latter step providing for the addressing, in succession, of all of the locations of the memory of which the memory cells have been programmed and, for each location addressed: a) the supply of an initial selection voltage definitely lower than the lowest threshold voltage to a line (WL; WL1-WL8) of the matrix (2; 20) corresponding to the location currently addressed, b) a reading of the cells of the location currently addressed with the use of reading circuits (SA; 21) of the memory, c) repetition of step b), progressively increasing the selection voltage supplied to the line (WL; WL1-WL8) of the matrix (2; 20) corresponding to the location currently addressed until it is detected that at least one of the bits of the location currently addressed has switched, the selection voltage for which the switching is detected being the lowest threshold voltage, d) comparison of the lowest threshold voltage of the location currently addressed with a stored value corresponding to the lowest of the lowest threshold voltages of the locations previously addressed, and e) storage of the lowest threshold voltage of the location currently addressed if it is lower than the stored value.
Abstract:
A state machine for generating signals configured for generating different signals according to the current state (SO, S1, S2, S3, IDLE) of the machine. The state machine is configured to change state both as a function of an internal timer (Cmp(n)) and as a function of signals (Edge(x); Edge (y)) representative of events external to the state machine.
Abstract:
A state machine for generating signals configured for generating different signals according to the current state (SO, S1, S2, S3, IDLE) of the machine. The state machine is configured to change state both as a function of an internal timer (Cmp(n)) and as a function of signals (Edge(x); Edge (y)) representative of events external to the state machine.
Abstract:
An integrated device (100) comprises at least one circuit element (Rp) and a plurality of trimming elements (Rti) which can be connected selectively to the at least one circuit element (Rp) in order to achieve a predetermined tolerance of a characteristic parameter of the at least one circuit element (Rp); the integrated device (100) includes a plurality of electronic switches (Mi), each of which can be switched between a first state and a second state in which it activates and deactivates a corresponding one of the trimming elements (Rti), respectively, and means (120) for storing an indication of the states of the electronic switches (Mi) and for operating each electronic switch (Mi) in the first state or in the second state according to the indication stored.