公开(公告)号：EP4373038A1

公开(公告)日：2024-05-22

申请号：EP23207659.6

申请日：2023-11-03

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： DONDINI, Mirko ,  TRECARICHI, Calogero Andrea ,  RENNIG, Fred

IPC: H04L12/40

CPC classification number: H04L12/40006 ,  H04L2012/4021520130101 ,  H04L2012/4027320130101

Abstract: A processing system (10a) is described. The processing system (10a) comprises a processing circuit (64), a volatile memory (60a) and a CAN communication controller circuit (50). The CAN communication controller circuit (50) comprises configuration and status registers (520). A transmission handler circuit (502) and a reception handler circuit (504) are configured to transmit and receive data via the CAN core circuit (500) by exchanging data with the volatile memory (60a) based on the configuration data stored to the configuration and status registers (520), and standard and/or extended filter elements stored to the volatile memory (60a).
Specifically, the processing system (10a) further comprises a hardware host circuit (62a) comprising a non-volatile memory (642) configured to store first configuration data (CD1) and second configuration data (CD2), wherein the first configuration data (CD1) comprise configuration data to be transferred to the configuration and status registers (520) of the CAN communication controller circuit (50) and the second configuration data (CD2) comprise at least one standard and/or extended filter element to be transferred to the volatile memory (60a). A control circuit (620, 628, 632) is configured to manage an initialization mode, a reception mode and a transmission mode. Specifically, during the initialization mode (648), the hardware host circuit (62a) stores the first configuration data (CD1) to the configuration and status registers (520) and the second configuration data (CD2) to the volatile memory (60a).

公开(公告)号：EP4246900A1

公开(公告)日：2023-09-20

申请号：EP23158838.5

申请日：2023-02-27

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o. ,  STMicroelectronics S.r.l.

Inventor： RENNIG, Fred ,  BARTHEL, Jochen ,  BERAN, Ludek ,  DONDINI, Mirko ,  DVORAK, Vaclav ,  POLISI, Vincenzo ,  SANZA', Marianna ,  TRECARICHI, Calogero Andrea ,  FURIO, Alfonso

IPC: H04L12/40 ,  G06F13/40 ,  G06F13/42

Abstract: A processing system (10a) is described. The processing system comprises a three-state driver circuit (502) and a CAN FD Light controller (500). The CAN FD Light controller (500) is configured to sequentially transmit the bits of a CAN FD Light frame, wherein the CAN FD Light frame comprises a start-of-frame bit (SOF), a sequence of bits (CD-EOF) comprising in sequence a Cyclic Redundancy Check, CRC, delimiter bit (CD), an acknowledge bit (AS), an acknowledge delimiter bit (AD) and an End-of-Frame field (EOF) having 7 bits, and a plurality of intermediate bits (SID-CRC) between said start-of-frame bit (SOF) and said CRC delimiter bit (CD).
In particular, the CAN FD Light controller (500) is configured to sequentially transmit the bits of the CAN FD Light frame via the three-state driver circuit (502) by using a push-pull configuration (CTRL1) when transmitting the start-of-frame bit (SOF) and the intermediate bits (SID-CRC). However, once having transmitted the intermediate bits (SID-CRC), the CAN FD Light controller (500) activates a high-impedance state (CTRL1) of the three-state driver circuit (502).

公开(公告)号：EP4002958A1

公开(公告)日：2022-05-25

申请号：EP21205675.8

申请日：2021-10-29

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

Inventor： TAGLIAVIA, Donato ,  POLISI, Vincenzo ,  TRECARICHI, Calogero Andrea ,  MAMMOLITI, Francesco Nino ,  BARTHEL, Jochen ,  BERAN, Ludek

IPC: H05B45/347 ,  H05B45/46 ,  H05B45/14

Abstract: A current supply system for strings of solid-state light sources (34) is disclosed. The current supply system comprises a plurality of terminals (OUT1..OUTn), wherein each of the terminals (OUT1..OUTn) is configured to be connected via a respective current regulator or limiter (32) to a first output terminal of a voltage source (20) and via a respective string of solid-state light sources (34) to a second output terminal of the voltage source (20). A control circuit (40) is configured to generate a reference signal ( V ref ) for the voltage source (20), wherein the reference signal is indicative of a requested output voltage ( V out ) to be generated by the voltage source (20) between the first and the second output terminals of the voltage source (20).
In particular, the control circuit (40) comprises:
- a digital feed-forward control circuit (408, 410, 412) configured to compute a digital feed-forward regulation value ( V out_req ) indicative of a requested output voltage by determining a maximum voltage drop ( V LED_MAX ) at the strings of solid-state light sources (34),
-a digital feed-back control circuit (414) configured to determine (1030) a minimum voltage drop ( V 32_MIN ) at the current regulators or limiters (32) and determine a digital feed-back correction value as a function of the minimum voltage drop ( V 32_MIN ), and
- a control circuit (40) configured to set the reference signal ( V ref ) after a start-up as a function of the digital feed-forward regulation value ( V out_req ) and then correct the reference signal ( V ref ) as a function of the digital feed-back correction value.

公开(公告)号：EP4012866A1

公开(公告)日：2022-06-15

申请号：EP21210682.7

申请日：2021-11-26

Applicant: STMicroelectronics S.r.l.

Inventor： CASTRO, Enrico ,  SUSINNA, Giovanni ,  RANDAZZO, Vincenzo ,  DONDINI, Mirko ,  TRECARICHI, Calogero Andrea

IPC: H02H3/087

Abstract: A current absorption management circuit (10) for use in an electronic fuse, for instance, comprises a first node (VBAT+) and a second node (OUT) coupled to an electrical supply source (for instance a battery SS in a motor vehicle V) and an electrical load (L) supplied by the electrical supply source (SS) via an electronic switch (such as a power MOSFET transistor 12) having a control node). A third node (GD) of the circuit is coupled to the electronic switch (12) to switch the electronic switch (12) between a conductive state (1000), wherein the electrical load (L) is coupled to the supply source (SS) via the electronic switch (12), and a non-conductive state (1000A).
A secondary electronic switch (12A) is arranged intermediate the first node (VBAT+) and the second node (OFF) and control logic circuitry (20) is provided configured to operate alternately:
in a first (full ON) mode of operation (1000), wherein the electronic switch (12) is in a conductive state and the electrical load (L) is coupled to the supply source (SS) via the electronic switch (12), and the secondary electronic switch (12A) is in a non-conductive state, and
in a second (ON active-standby) mode of operation (1002), wherein the electronic switch (12) is in a non-conductive state and the secondary electronic switch (12A) is in a conductive state and the electrical load (L) is coupled to the supply source (SS) via the secondary electronic switch (12A).

公开(公告)号：EP3961229A1

公开(公告)日：2022-03-02

申请号：EP21190380.2

申请日：2021-08-09

Applicant: STMicroelectronics S.r.l.

Inventor： DONDINI, Mirko ,  CRISAFULLI, Roberto ,  TRECARICHI, Calogero Andrea ,  RANDAZZO, Vincenzo

IPC: G01R31/3167 ,  G01R31/317

Abstract: An electronic device (10) such as an e-fuse comprises analog circuitry configured to be set to one or more self-test configurations. To that effect the device comprises self-test controller circuitry (12) in turn comprising:
an analog configuration and sensing circuit (16, 162) configured to set the analog circuitry to one or more self-test configurations and to sense test signals occurring in the analog circuitry set to such self-test configurations,
a data acquisition circuit (18, 182) configured to acquire and convert to digital the test signals sensed at the analog sensing circuit, and
a fault event detection circuit (22, 222) configured to check the test signals converted to digital against reference parameters.
The device (10) comprises integrated therein a self-test controller (12) configured to control parts or stages of the device to configure circuits, acquire data and control test execution under the coordination of a test sequencer (120).