公开(公告)号：US20240113251A1

公开(公告)日：2024-04-04

申请号：US18519778

申请日：2023-11-27

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur

IPC: H01L33/00 ,  H01L31/0224 ,  H01L31/0304 ,  H01L31/0352 ,  H01L31/105 ,  H01L31/109 ,  H01L33/02 ,  H01L33/04 ,  H01L33/14 ,  H01L33/32

CPC classification number: H01L33/002 ,  H01L31/022408 ,  H01L31/03048 ,  H01L31/0352 ,  H01L31/035236 ,  H01L31/105 ,  H01L31/109 ,  H01L33/0025 ,  H01L33/025 ,  H01L33/04 ,  H01L33/14 ,  H01L33/145 ,  H01L33/32 ,  H01L33/06 ,  H01L2933/0008

Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The heterostructure can include a p-type interlayer located between the electron blocking layer and the p-type contact layer. In an embodiment, the electron blocking layer can have a region of graded transition. The p-type interlayer can also include a region of graded transition.

公开(公告)号：US11508871B2

公开(公告)日：2022-11-22

申请号：US17060954

申请日：2020-10-01

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur

IPC: H01L33/00 ,  H01L33/32 ,  H01L31/0352 ,  H01L33/14 ,  H01L31/105 ,  H01L31/0224 ,  H01L31/0304 ,  H01L33/02 ,  H01L31/109 ,  H01L33/04 ,  H01L33/06

Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The electron blocking layer is located between the active region and the p-type contact layer. In an embodiment, the electron blocking layer can include a plurality of sublayers that vary in composition.

公开(公告)号：US10804423B2

公开(公告)日：2020-10-13

申请号：US15966022

申请日：2018-04-30

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur

IPC: H01L31/0352 ,  H01L33/00 ,  H01L31/105 ,  H01L31/0224 ,  H01L33/32 ,  H01L33/04 ,  H01L33/14 ,  H01L33/02 ,  H01L31/0304 ,  H01L31/109 ,  H01L33/06

Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.

公开(公告)号：US10460952B2

公开(公告)日：2019-10-29

申请号：US16022939

申请日：2018-06-29

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Jinwei Yang ,  Wenhong Sun ,  Rakesh Jain ,  Michael Shur ,  Remigijus Gaska

IPC: H01L21/308 ,  H01L29/20 ,  H01L21/02 ,  H01L29/66 ,  H01L29/15 ,  H01L33/00 ,  H01L33/12 ,  H01L33/22 ,  H01L33/32

Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

公开(公告)号：US10211048B2

公开(公告)日：2019-02-19

申请号：US13756806

申请日：2013-02-01

Applicant: Sensor Electronic Technology, Inc.

Inventor： Wenhong Sun ,  Rakesh Jain ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Remigijus Gaska ,  Michael Shur

IPC: H01L21/02 ,  H01L29/06 ,  H01L33/00 ,  H01L33/12 ,  H01L33/16

Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer. One or more of a set of growth conditions, a thickness of one or both of the layers, and/or a lattice mismatch between the layers can be configured to create a target level of compressive and/or shear stress within a minimum percentage of the interface between the layers.

公开(公告)号：US20190006553A1

公开(公告)日：2019-01-03

申请号：US16022856

申请日：2018-06-29

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov

IPC: H01L33/00 ,  H01L31/18 ,  C23C16/56 ,  C23C16/02 ,  C23C16/34 ,  C30B25/18 ,  C30B29/40

Abstract: Semiconductor structures formed with annealing for use in the fabrication of optoelectronic devices. The semiconductor structures can include a substrate, a nucleation layer and a buffer layer. The nucleation layer and the buffer layer can be epitaxially grown and then annealed. The temperature of the annealing of the nucleation layer and the buffer layer is greater than the temperature of the epitaxial growth of the layers. The annealing reduces the dislocation density in any subsequent layers that are added to the semiconductor structures. A desorption minimizing layer epitaxially grown on the buffer layer can be used to minimize desorption during the annealing of the layer which also aids in curtailing dislocation density and cracks in the semiconductor structures.

公开(公告)号：US20180323071A1

公开(公告)日：2018-11-08

申请号：US16022939

申请日：2018-06-29

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Jinwei Yang ,  Wenhong Sun ,  Rakesh Jain ,  Michael Shur ,  Remigijus Gaska

IPC: H01L21/308 ,  H01L21/02 ,  H01L29/66 ,  H01L29/20 ,  H01L29/15 ,  H01L33/12 ,  H01L33/00

Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

公开(公告)号：US20180269355A1

公开(公告)日：2018-09-20

申请号：US15989275

申请日：2018-05-25

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/12

CPC classification number: H01L33/12 ,  C30B25/04 ,  C30B25/183 ,  C30B29/406 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/518 ,  H01L29/7786 ,  H01L29/7787 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/10 ,  H01L33/145 ,  H01L33/22 ,  H01L33/24 ,  H01L33/32 ,  H01L33/405 ,  H01L2933/0091

Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.

公开(公告)号：US10050175B2

公开(公告)日：2018-08-14

申请号：US15797263

申请日：2017-10-30

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L27/15 ,  H01L31/072 ,  H01L33/06 ,  H01L21/02 ,  H01L29/778 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L29/20 ,  H01L29/51 ,  H01L33/22

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

公开(公告)号：US09911895B2

公开(公告)日：2018-03-06

申请号：US15069178

申请日：2016-03-14

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Alexander Dobrinsky ,  Alexander Lunev ,  Rakesh Jain ,  Jinwei Yang ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/00 ,  H01L33/32 ,  H01L33/10 ,  H01L33/46 ,  H01S5/022

CPC classification number: H01L33/0025 ,  H01L33/0075 ,  H01L33/10 ,  H01L33/32 ,  H01L33/46 ,  H01S5/0224

Abstract: A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher.