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    Apparatus and process for bare chip test and burn-in
    4.
    发明公开
    Apparatus and process for bare chip test and burn-in 失效
    Apparat und Verfahren zum Chiptest和Einbrennen。

    公开(公告)号：EP0600604A1

    公开(公告)日：1994-06-08

    申请号：EP93308531.8

    申请日：1993-10-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Chiu, Anthony M.

    IPC: G01R1/04 ,  G01R31/28

    CPC classification number: G01R1/0483

    Abstract: The invention is to an apparatus and method for testing and burn-in of bare semiconductor chips. A molded chip carrier (10) of a high temperature plastic is utilized as a temporary holder for the chip. The carrier also has three alignment holes (15, 16, 119) that correspond to the alignment pins (24, 25, 27) in a test socket (20). The contact pads on the chip are aligned to contacts in the test socket (20) utilizing the alignment holes and pins. Before starting the testing and burn-in process, the carrier (10) with a chip is loaded into the socket (20), with the contact pads on the chip facing the tips of the contact elements in the socket. The carrier (10) is inserted into the socket (20) using the alignment pins (24, 25, 27) and holes (15, 16, 19) as guides. Clamping force is applied by the lid to ensure that the contacts of the socket maintain adequate contact force with the device contact pads during burn-in and testing. After burn-in and testing, the carrier (10) with the chip attached to it is removed from the socket (20).

    Abstract translation: 本发明是用于裸半导体芯片的测试和老化的装置和方法。 利用高温塑料的模制芯片载体（10）作为芯片的临时保持器。 载体还具有对应于测试插座（20）中的对准销（24,25,27）的三个对准孔（15,16,119）。 利用对准孔和引脚，芯片上的接触焊盘与测试插座（20）中的触点对准。 在开始测试和老化过程之前，具有芯片的载体（10）被加载到插座（20）中，芯片上的接触垫面对插座中的接触元件的尖端。 使用对准销（24,25,27）和作为引导件的孔（15,16,19）将托架（10）插入到插座（20）中。 通过盖子施加夹紧力，以确保在插入和测试期间插座的触点与设备接触垫保持足够的接触力。 在老化和测试之后，将带有芯片的载体（10）从插座（20）中取出。

    Chip on board assembly
    5.
    发明公开
    Chip on board assembly 失效
    芯片Direktmontage。

    公开(公告)号：EP0590915A1

    公开(公告)日：1994-04-06

    申请号：EP93307645.7

    申请日：1993-09-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Chiu, Anthony M.

    IPC: H01L25/065 ,  H01L23/538

    CPC classification number: H01L24/05 ,  H01L23/5384 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/48599 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/85399

    Abstract: A chip-on-board assembly and a method of making is described in which semiconductor chips (32) having center contacts (35) are mounted active side down on the circuit board (31) with the center contacts (35) centered in an elongated opening (33) in the circuit board (31). The center contacts (35) are connected through the openings (33) in the circuit board (31) to contacts (34) on the circuit board (31) on the opposite side of the circuit board (31) on which the semiconductor chip (32) is mounted. Semiconductor chips (32) are alternately mounted on opposite sides of the circuit board (31) to provide a higher placement density of semiconductor chips.

    Abstract translation: 描述了一种片上组装和制造方法，其中具有中心触点（35）的半导体芯片（32）主动侧安装在电路板（31）上，中心触点（35）以细长的 在电路板（31）中的开口（33）。 中心触点（35）通过电路板（31）中的开口（33）连接到电路板（31）的与半导体芯片（31）相反侧上的触点（34） 32）。 半导体芯片（32）交替地安装在电路板（31）的相对侧上，以提供更高的半导体芯片的放置密度。

    Wafer burn-in and test system and method of making the same
    9.
    发明公开
    Wafer burn-in and test system and method of making the same 失效
    Prüf-und Einbrennsystemfüreinen Wafer。

    公开(公告)号：EP0494782A1

    公开(公告)日：1992-07-15

    申请号：EP92300190.3

    申请日：1992-01-09

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Chiu, Anthony M.

    IPC: H01L21/66 ,  G01R31/28

    CPC classification number: G01R31/2856 ,  G01R31/2863

    Abstract: An interconnection system and method of testing and performing burn-in semiconductor devices (12) prior to separation from the semiconductor wafer on which the devices are formed includes forming interconnection layers of contacts (16) and conductors (17) over the devices and then testing and performing burn-in on the devices. Faulty devices are disconnected from the conductors prior to performing additional test and burn-in. The interconnections are removed prior to separating the device on the wafer, and prior to further possible tests and packaging.

    Abstract translation: 在与形成器件的半导体晶片分离之前测试和执行老化半导体器件（12）的互连系统和方法包括在器件上形成触点（16）和导体（17）的互连层，然后测试 并在设备上执行老化。 在进行额外的测试和老化之前，故障设备与导体断开连接。 在将器件分离在晶片上之前，以及在进一步可能的测试和封装之前，互连被去除。

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