公开(公告)号：CN100544544C

公开(公告)日：2009-09-23

申请号：CN200710200565.4

申请日：2007-04-29

Applicant: 佛山普立华科技有限公司 ,  鸿海精密工业股份有限公司

Inventor： 侯震 ,  王境良

IPC: H05K1/02 ,  H01R12/00

CPC classification number: H01R43/0256 ,  H05K1/116 ,  H05K3/3447 ,  H05K2201/09463 ,  H05K2201/09709 ,  H05K2201/10689 ,  H05K2201/10696

Abstract: 本发明提供一种直插式芯片焊座，其包括一个具有一个焊接面的基板、至少一个开设于所述焊接面的插设部及至少一个形成于所述焊接面的焊盘组。每个插设部用于收容待组装直插式芯片的一列插脚，每个焊盘组包括多个位于对应插设部边缘的焊盘，用于焊接待组装直插式芯片的一列插脚。同个焊盘组中，用于焊接待组装直插式芯片相邻两只插脚的两个焊盘分别位于对应插设部的两侧。所述直插式芯片焊座用于焊接待组装直插式芯片相邻两只插脚的两个焊盘分布于对应插设部的两侧。如此，可增大焊盘间距，避免焊盘焊接插脚时发生端接现象，造成插脚短路。另外，本发明还提供一种采用所述直插式芯片焊座的直插式芯片组装结构。

公开(公告)号：CN101296560A

公开(公告)日：2008-10-29

申请号：CN200710200565.4

申请日：2007-04-29

Applicant: 佛山普立华科技有限公司 ,  鸿海精密工业股份有限公司

Inventor： 侯震 ,  王境良

IPC: H05K1/02 ,  H01R12/00

CPC classification number: H01R43/0256 ,  H05K1/116 ,  H05K3/3447 ,  H05K2201/09463 ,  H05K2201/09709 ,  H05K2201/10689 ,  H05K2201/10696

Abstract: 本发明提供一种直插式芯片焊座，其包括一个具有一个焊接面的基板、至少一个开设于所述焊接面的插设部及至少一个形成于所述焊接面的焊盘组。每个插设部用于收容待组装直插式芯片的一列插脚，每个焊盘组包括多个位于对应插设部边缘的焊盘，用于焊接待组装直插式芯片的一列插脚。同个焊盘组中，用于焊接待组装直插式芯片相邻两只插脚的两个焊盘分别位于对应插设部的两侧。所述直插式芯片焊座用于焊接待组装直插式芯片相邻两只插脚的两个焊盘分布于对应插设部的两侧。如此，可增大焊盘间距，避免焊盘焊接插脚时发生端接现象，造成插脚短路。另外，本发明还提供一种采用所述直插式芯片焊座的直插式芯片组装结构。

公开(公告)号：JP2007134697A

公开(公告)日：2007-05-31

申请号：JP2006281543

申请日：2006-10-16

Applicant: Honeywell Internatl Inc ,  ハネウェル・インターナショナル・インコーポレーテッド

Inventor： MCCARTHY DANIEL J ,  WITHANAWASAM LAKSHMAN S

IPC: H01L23/12 ,  H01L25/04 ,  H01L25/18

CPC classification number: H01L23/3121 ,  H01L21/4846 ,  H01L23/49805 ,  H01L25/105 ,  H01L2224/48247 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1064 ,  H05K3/3442 ,  H05K2201/10454 ,  H05K2201/10696 ,  Y02P70/613

Abstract: PROBLEM TO BE SOLVED: To provide a method of fabricating a vertically mountable integrated circuit (IC) package. SOLUTION: The method is provided for fabricating the vertically mountable integrated circuit (IC). The integrated circuit is mounted on a printed circuit board (PCB) and is electrically connected to bond pads on the PCB. The bond pads are connected to vias embedded in the PCB. The IC, bond pads, vias, and PCB are partially divided to form the vertically mountable IC package. When divided, the vias are cut across to be partially exposed, so that a mountable area is provided for the IC package. The IC package is sealed or stored in a dielectric material. Further, the vias are treated with a preservative for preventing oxidation and improving solderability or other suitable deposits of electroless metal plating. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造可垂直安装的集成电路（IC）封装的方法。 解决方案：该方法用于制造可垂直安装的集成电路（IC）。 集成电路安装在印刷电路板（PCB）上，并电连接到PCB上的接合焊盘。 接合焊盘连接到嵌入PCB中的通孔。 IC，接合焊盘，通孔和PCB被部分地分开以形成可垂直安装的IC封装。 当分开时，通孔被切割以部分暴露，使得为IC封装提供可安装区域。 IC封装被密封或存储在电介质材料中。 此外，用防腐剂处理通孔以防止氧化和改善可焊性或其它合适的无电镀金属沉积物。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：EP0844811B1

公开(公告)日：2004-09-22

申请号：EP97850147.6

申请日：1997-10-24

Applicant: Infineon Technologies AG

Inventor： Hellgren, Eva ,  Eriksson, Mats

IPC: H05K7/08 ,  H05K13/04

CPC classification number: H05K3/366 ,  H05K3/303 ,  H05K13/046 ,  H05K2201/10386 ,  H05K2201/10454 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/613

公开(公告)号：EP0682366A3

公开(公告)日：1996-03-06

申请号：EP95107226.3

申请日：1995-05-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Russell, Ernest ,  Wallace, James S. ,  Baudouin, Daniel

IPC: H01L23/32 ,  H01L23/48 ,  H05K1/18 ,  H01L25/10 ,  H01L23/495 ,  H05K3/30

CPC classification number: H05K1/181 ,  H01L23/32 ,  H01L23/49555 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1082 ,  H01L2924/0002 ,  H05K3/303 ,  H05K2201/10454 ,  H05K2201/10545 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

Abstract: Two flat packages (110, 111) are arranged to achieve a mirrored footprint by employing guides (100), which are positioned within a mounting aperture a printed circuit board. The flat packages include leads (120,121) which extend from the edge of the flat package. A semiconductor chip is encapsulated by the flat packages.

公开(公告)号：EP0520490B1

公开(公告)日：1995-01-25

申请号：EP92110825.4

申请日：1992-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： McLellan, Robert N. ,  Chiu, Anthony M.

IPC: H05K3/30 ,  H01L23/495

CPC classification number: H05K3/301 ,  H01L23/49555 ,  H01L2924/0002 ,  H05K3/303 ,  H05K2201/10454 ,  H05K2201/10568 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T29/49121 ,  Y10T29/49139 ,  H01L2924/00

公开(公告)号：EP0333374A2

公开(公告)日：1989-09-20

申请号：EP89302297.0

申请日：1989-03-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Baudouin, Daniel A. ,  Russell, Ernest J.

IPC: H05K3/30 ,  H01L23/50 ,  H01L23/495 ,  H01L23/04

CPC classification number: H05K3/303 ,  H01L23/49555 ,  H01L2924/0002 ,  H05K2201/10454 ,  H05K2201/10568 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2924/00

Abstract: A flat package (10) for semiconductor integrated circuit devices allows edge-mounting and surface-mount. The package may be molded plastic (12) containing a semiconductor chip (11), and flat leads (14) extend from one edge of the package. The leads are bent to provide an area (18) to solder to conductors on a PC board. Mechanical positioning, mechanical support and spacing are provided by studs (15) extending from the edge of the package adjacent the leads. The studs have stops (17) formed at a position even with flat outer surfaces of the bent leads; the portion outward of the stops fits into holes in the PC board.

Abstract translation: 用于半导体集成电路器件的扁平封装（10）允许边缘安装和表面贴装。 封装可以是包含半导体芯片（11）的模制塑料（12），并且扁平引线（14）从封装的一个边缘延伸。 引线被弯曲以提供焊接到PC板上的导体的区域（18）。 机械定位，机械支撑和间距由靠近引线的封装边缘延伸的螺柱（15）提供。 螺栓具有形成在即使具有弯曲引线的平坦外表面的位置的止动件（17） 止动件外侧的部分装配到PC板中的孔中。

公开(公告)号：EP1775767A3

公开(公告)日：2008-02-20

申请号：EP06122283.2

申请日：2006-10-13

Applicant: Honeywell International Inc.

Inventor： MCCARTHY, Daniel J. ,  WITHANAWASAM, Lakshman S.

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/3121 ,  H01L21/4846 ,  H01L23/49805 ,  H01L25/105 ,  H01L2224/48247 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1064 ,  H05K3/3442 ,  H05K2201/10454 ,  H05K2201/10696 ,  Y02P70/613

Abstract: A method of fabricating a vertically mountable integrated circuit (IC) package is presented. An integrated circuit is mounted on a printed circuit board (PCB) and electrically coupled to a bond pad on the PCB. The bond pad is coupled with a via that is embedded in the PCB. A portion of the PCB comprising the IC, the bond pad and the via is separated in order to create a vertically mountable IC package. The via is cut through cross-sectionally during singulation so as to expose a portion of the via and thereby provide a mountable area for the IC package. The IC package may be encapsulated or housed in a dielectric material. In addition, the via may be treated with a preservative or other suitable electroless metal plating deposition that prevents oxidation and promotes solderability.

公开(公告)号：EP1775767A2

公开(公告)日：2007-04-18

申请号：EP06122283.2

申请日：2006-10-13

Applicant: Honeywell International Inc.

Inventor： MCCARTHY, Daniel J. ,  WITHANAWASAM, Lakshman S.

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/3121 ,  H01L21/4846 ,  H01L23/49805 ,  H01L25/105 ,  H01L2224/48247 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1064 ,  H05K3/3442 ,  H05K2201/10454 ,  H05K2201/10696 ,  Y02P70/613

Abstract: A method of fabricating a vertically mountable integrated circuit (IC) package is presented. An integrated circuit is mounted on a printed circuit board (PCB) and electrically coupled to a bond pad on the PCB. The bond pad is coupled with a via that is embedded in the PCB. A portion of the PCB comprising the IC, the bond pad and the via is separated in order to create a vertically mountable IC package. The via is cut through cross-sectionally during singulation so as to expose a portion of the via and thereby provide a mountable area for the IC package. The IC package may be encapsulated or housed in a dielectric material. In addition, the via may be treated with a preservative or other suitable electroless metal plating deposition that prevents oxidation and promotes solderability.

Abstract translation: 提出了制造可垂直安装的集成电路（IC）封装的方法。 集成电路安装在印刷电路板（PCB）上并电耦合到PCB上的接合焊盘。 接合焊盘与嵌入在PCB中的通孔耦合。 包括IC，接合焊盘和通孔的PCB的一部分被分离以产生可垂直安装的IC封装。 在分割期间，通孔横截面切割，以暴露通孔的一部分，从而为IC封装提供可安装区域。 IC封装可以被封装或容纳在电介质材料中。 此外，通孔可以用防腐剂或其它合适的无电金属电镀沉积进行处理，防止氧化并促进可焊性。

公开(公告)号：EP0460559A2

公开(公告)日：1991-12-11

申请号：EP91109004.1

申请日：1991-06-02

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Takahashi, Hiroyuki

IPC: H01G2/06 ,  H03H9/10

CPC classification number: H01G2/06 ,  H03H9/0528 ,  H03H9/1042 ,  H05K1/0271 ,  H05K3/308 ,  H05K3/3447 ,  H05K2201/10651 ,  H05K2201/10696 ,  H05K2201/10871

Abstract: A radial lead type electronic component (4) includes a couple of plate-type lead terminals (1,2,3) projecting from a protective resin member (9) in the same direction. These lead terminals (1,2,3) are provided with inclined edges (1d,1e;2d,2e), which make the body portions (1c-3c) gradually narrowed toward leg portions (1a-3a), in leg-side edges of body portions. Among inclined edges, inclinations ϑ ₁ of the outer ones with respect to the leg-projecting direction are greater than inclinations ϑ ₂ of the inner ones with respect to the same direction.

Abstract translation: 径向引线型电子部件（4）包括从保护性树脂部件（9）向相同方向突出的一对板状引线端子（1,2,3）。 这些引线端子（1,2,3）设置有倾斜边缘（1d，1e; 2d，2e），其使得主体部分（1c-3c）朝向腿部（1a-3a）逐渐变窄， 身体部分的边缘。 在倾斜边缘中，外侧相对于腿部伸出方向的倾斜度θ1大于相对于相同方向的内侧倾斜度θ2。