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    MANUFACTURING METHOD OF INTERPOSED SUBSTRATE
    3.
    发明申请
    MANUFACTURING METHOD OF INTERPOSED SUBSTRATE 审中-公开
    嵌入式基板的制造方法

    公开(公告)号：US20160133483A1

    公开(公告)日：2016-05-12

    申请号：US14995207

    申请日：2016-01-14

    Applicant: Unimicron Technology Corp.

    Inventor： Dyi-Chung Hu ,  Ming-Chih Chen ,  Tzyy-Jang Tseng

    IPC: H01L21/48 ,  C25D5/34 ,  C25D5/48 ,  C25D7/12 ,  C25D5/02

    CPC classification number: H01L21/4857 ,  C25D1/003 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  C25D7/12 ,  H05K1/113 ,  H05K3/10 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0733 ,  Y10T29/49155

    Abstract: A manufacturing method of an interposed substrate is provided. A metal-stacked layer comprising a first metal layer, an etching stop layer and a second metal layer is formed. A patterned conductor layer is formed on the first metal layer, wherein the patterned conductor layer exposes a portion of the first metal layer. A plurality of conductive pillars is formed on the patterned conductor layer, wherein the conductive pillars are separated from each other and stacked on a portion of the patterned conductor layer. An insulating material layer is formed on the metal-stacked layer, wherein the insulating material layer covers the portion of the first metal layer and encapsulates the conductive pillars and the other portion of the patterned conductor layer. The metal-stacked layer is removed to expose a lower surface opposite to an upper surface of the insulating material layer and a bottom surface of the patterned conductor layer.

    Abstract translation: 提供了一种插入式基板的制造方法。 形成包括第一金属层，蚀刻停止层和第二金属层的金属层叠层。 图案化的导体层形成在第一金属层上，其中图案化的导体层露出第一金属层的一部分。 在图案化的导体层上形成多个导电柱，其中导电柱彼此分离并堆叠在图案化的导体层的一部分上。 在金属堆叠层上形成绝缘材料层，其中绝缘材料层覆盖第一金属层的部分并且封装导电柱和图案化导体层的另一部分。 去除金属层叠层以露出与绝缘材料层的上表面相反的下表面和图案化导体层的底表面。

    MANUFACTURING METHOD OF INTERPOSED SUBSTRATE
    4.
    发明申请
    MANUFACTURING METHOD OF INTERPOSED SUBSTRATE 审中-公开
    嵌入式基板的制造方法

    公开(公告)号：US20150097318A1

    公开(公告)日：2015-04-09

    申请号：US14568084

    申请日：2014-12-11

    Applicant: Unimicron Technology Corp.

    Inventor： Dyi-Chung Hu ,  Ming-Chih Chen ,  Tzyy-Jang Tseng

    IPC: H01L21/48

    CPC classification number: H01L21/481 ,  C25D1/003 ,  H05K1/113 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0726 ,  H05K2203/0733 ,  Y10T29/49155 ,  Y10T156/10

    Abstract: A manufacturing method of an interposed substrate is provided. A photoresist layer is formed on a metal carrier. The photoresist layer has plural of openings exposing a portion of the metal carrier. Plural of metal passivation pads and plural of conductive pillars are formed in the openings. The metal passivation pads cover a portion of the metal carrier exposed by openings. The conductive pillars are respectively stacked on the metal passivation pads. The photoresist layer is removed to expose another portion of the metal carrier. An insulating material layer is formed on the metal cattier. The insulating material layer covers the another portion of the metal carrier and encapsulates the conductive pillars and the metal passivation pads.An upper surface of the insulating material layer and a top surface of each conductive pillar are coplanar. The metal carrier is removed to expose a lower surface of the insulating material layer.

    Abstract translation: 提供了一种插入式基板的制造方法。 在金属载体上形成光致抗蚀剂层。 光致抗蚀剂层具有暴露金属载体的一部分的多个开口。 多个金属钝化垫和多个导电柱形成在开口中。 金属钝化垫覆盖由开口暴露的金属载体的一部分。 导电柱分别堆叠在金属钝化垫上。 去除光致抗蚀剂层以暴露金属载体的另一部分。 在金属罐上形成绝缘材料层。 绝缘材料层覆盖金属载体的另一部分并封装导电柱和金属钝化垫。 绝缘材料层的上表面和每个导电柱的顶表面是共面的。 去除金属载体以暴露绝缘材料层的下表面。

    INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    互连结构及其制造方法

    公开(公告)号：US20160268206A1

    公开(公告)日：2016-09-15

    申请号：US14644197

    申请日：2015-03-10

    Applicant: Unimicron Technology Corp.

    Inventor： Dyi-Chung Hu ,  Yin-Po Hung ,  Ra-Min Tain ,  Yu-Hua Chen

    IPC: H01L23/538 ,  H01L21/768

    CPC classification number: H01L21/76879 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827

    Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a substrate, a conductive through via, a dielectric layer, and a conductive layer. The substrate has a first surface and a second surface opposite to each other. The conductive through via is disposed in the substrate and extended from the first surface beyond the second surface. The dielectric layer is disposed on the substrate, wherein the dielectric layer has an opening exposing a portion of the conductive through via. The top surface of the conductive through via protrudes from the bottom surface of the opening. The conductive layer is disposed in the opening and connected to the conductive through via.

    Abstract translation: 提供互连结构及其制造方法。 互连结构包括衬底，导电通孔，电介质层和导电层。 基板具有彼此相对的第一表面和第二表面。 导电通孔设置在基板中并从第一表面延伸超过第二表面。 介电层设置在基板上，其中电介质层具有露出导电通孔的一部分的开口。 导电通孔的顶表面从开口的底表面突出。 导电层设置在开口中并连接到导电通孔。

    Packaging carrier and manufacturing method thereof and chip package structure
    7.
    发明授权
    Packaging carrier and manufacturing method thereof and chip package structure 有权
    包装载体及其制造方法及芯片封装结构

    公开(公告)号：US09374896B2

    公开(公告)日：2016-06-21

    申请号：US14038769

    申请日：2013-09-27

    Applicant: Unimicron Technology Corp.

    Inventor： Ming-Chih Chen ,  Dyi-Chung Hu

    IPC: H05K1/16 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46

    CPC classification number: H05K1/113 ,  H01L2224/16225 ,  H01L2924/15174 ,  H05K3/4038 ,  H05K3/4602 ,  H05K2201/10378 ,  Y10T29/49149

    Abstract: A packaging carrier includes an interposer, a dielectric layer and a built-up structure. The interposer has a first surface and a second surface opposite to each other, and a plurality of first pads and second pads located on the first surface and the second surface, respectively. The dielectric layer has a third surface and a fourth surface opposite to each other. The interposer is embedded in the dielectric layer. The second surface of the interposer is not covered by the fourth surface of the dielectric layer, and has a height difference with the fourth surface. The built-up structure is disposed on the third surface of the dielectric layer and electrically connected to the first pads of the interposer.

    Abstract translation: 包装载体包括插入件，电介质层和积层结构。 插入器具有彼此相对的第一表面和第二表面，以及分别位于第一表面和第二表面上的多个第一焊盘和第二焊盘。 电介质层具有彼此相对的第三表面和第四表面。 插入器嵌入电介质层。 插入器的第二表面不被电介质层的第四表面覆盖，并且与第四表面具有高度差。 积层结构设置在电介质层的第三表面上并电连接到插入器的第一焊盘。

    PACKAGING CARRIER AND MANUFACTURING METHOD THEREOF AND CHIP PACKAGE STRUCTURE
    8.
    发明申请
    PACKAGING CARRIER AND MANUFACTURING METHOD THEREOF AND CHIP PACKAGE STRUCTURE 有权
    包装载体及其制造方法和芯片包装结构

    公开(公告)号：US20140102772A1

    公开(公告)日：2014-04-17

    申请号：US14038769

    申请日：2013-09-27

    Applicant: Unimicron Technology Corp.

    Inventor： Ming-Chih Chen ,  Dyi-Chung Hu

    IPC: H05K1/11 ,  H05K3/40

    CPC classification number: H05K1/113 ,  H01L2224/16225 ,  H01L2924/15174 ,  H05K3/4038 ,  H05K3/4602 ,  H05K2201/10378 ,  Y10T29/49149

    Abstract: A packaging carrier includes an interposer, a dielectric layer and a built-up structure. The interposer has a first surface and a second surface opposite to each other, and a plurality of first pads and second pads located on the first surface and the second surface, respectively. The dielectric layer has a third surface and a fourth surface opposite to each other. The interposer is embedded in the dielectric layer. The second surface of the interposer is not covered by the fourth surface of the dielectric layer, and has a height difference with the fourth surface. The built-up structure is disposed on the third surface of the dielectric layer and electrically connected to the first pads of the interposer.

    Abstract translation: 包装载体包括插入件，电介质层和积层结构。 插入器具有彼此相对的第一表面和第二表面，以及分别位于第一表面和第二表面上的多个第一焊盘和第二焊盘。 电介质层具有彼此相对的第三表面和第四表面。 插入器嵌入电介质层。 插入器的第二表面不被电介质层的第四表面覆盖，并且与第四表面具有高度差。 积层结构设置在电介质层的第三表面上并电连接到插入器的第一焊盘。

    PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME
    10.
    发明申请
    PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210066189A1

    公开(公告)日：2021-03-04

    申请号：US17095742

    申请日：2020-11-12

    Applicant: Industrial Technology Research Institute ,  Unimicron Technology Corp.

    Inventor： Yu-Hua Chen ,  Wei-Chung Lo ,  Dyi-Chung Hu ,  Chang-Hong HSIEH

    IPC: H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L25/04

    Abstract: A package substrate includes a substrate, an interposer and an insulating protective layer. The substrate has a first surface and a second surface opposing to the first surface. The first surface includes a plurality of first conductive pads. The interposer is disposed on the first surface of the substrate such that the first conductive pads are partially covered by the interposer. The interposer includes a plurality of penetrating conductive vias electrically connected to the substrate. The insulating protective layer is disposed on the first surface of the substrate and surrounding the interposer. The insulating protective layer includes at least one penetrating conductive column, wherein a first width of the respective penetrating conductive column is greater than a second width of each of the penetrating conductive vias of the interposer.

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