公开(公告)号：KR1020140036503A

公开(公告)日：2014-03-26

申请号：KR1020120102644

申请日：2012-09-17

Applicant: 금오공과대학교 산학협력단

Inventor： 장영찬 ,  김문규 ,  정훈주

IPC: H03M1/66

CPC classification number: H03M1/661 ,  H03M1/82 ,  H03M2201/32 ,  H03M2201/6185 ,  H03M2201/625

Abstract: The present invention relates to a technology which improves resolution by controlling the transient time to an analog level using a time-interpolation method in a digital-analog converter and suppresses the consequent increase in the area. The present invention includes a m-bit time-interpolation unit for receiving analog signals VREF(k) and VREF(k+1) supplied through (n-m)-bit reference voltage resistor column and (n-m)-bit first and second decoders, performing time-interpolation which controls the transient time from one analog level to other analog level, and outputting an analog signal (VC) having its resolution increased by m-bit. [Reference numerals] (120A) (n-m) bit decoder; (130) m-bit time-interpolation unit

Abstract translation: 本发明涉及通过使用数字 - 模拟转换器中的时间插值方法来控制模拟电平的瞬态时间来提高分辨率的技术，并且抑制了随之而来的增加的面积。 本发明包括一个m位时间插值单元，用于接收通过（nm）位参考电压电阻列和（nm）位第一和第二解码器提供的模拟信号VREF（k）和VREF（k + 1），执行 时间插值控制从一个模拟电平到其他模拟电平的瞬态时间，并输出其分辨率增加了m位的模拟信号（VC）。 （参考号）（120A）（n-m）比特解码器; （130）m位时间插值单元

公开(公告)号：KR1020060091847A

公开(公告)日：2006-08-22

申请号：KR1020050012564

申请日：2005-02-16

Applicant: 김윤정 ,  임신일 ,  김석기

Inventor： 김윤정 ,  김석기 ,  임신일

IPC: H03M1/12

CPC classification number: H03M1/203 ,  H03M1/002 ,  H03M2201/6185 ,  H03M2201/625 ,  H03M2201/933

Abstract: 아날로그-디지털 변환기에서 인터폴레이션 엠프의 갯수를 줄이기 위한 새로운 구조의 비교기의 프리엠프를 제안한다.
아날로그-디지털 변환기, 비교기, 인터폴레이션 기법, 4x 인터폴레이션 포인트

公开(公告)号：KR200301508Y1

公开(公告)日：2003-01-24

申请号：KR2020020021570

申请日：2002-07-19

Applicant: 박성백

Inventor： 박성백

IPC: H03M1/12

CPC classification number: H03M1/202 ,  H03M2201/192 ,  H03M2201/6185

Abstract: 본 고안은 온도계, 습도계, 미터계 및 제어장치 등에 사용되는 원칩마이컴을 이용한 아날로그/디지털(이하 'A/D'라 함) 컨버터에 관한 것으로, 더욱 상세하게는 A/D 컨버터가 내장된 마이컴의 출력 비트수로는 구현될 수 없는 A/D 컨버터의 출력값을 마이컴의 내부 출력과 저항과 콘덴서 및 마이컴 내부에서 수행되는 특정 내부프로그램을 이용하거나 상기 내부 프로그램만을 이용하여 정확하고 안정되게 확장시켜, 별도의 추가 비용없이 온도계, 습도계, 미터계, 기타 제어장치 등을 보다 정밀하게 제어하고 계측량을 넓혀 사용할 수 있게 하는 출력값의 확장이 가능한 A/D 컨버터에 관한 것이다.
본 고안에 따르면, A/D 컨버터와 결합되는 원칩마이컴에서 수행되는 내부 프로그램과, 원칩마이컴에 저항이 직렬로 접속되고 상기 저항에 콘덴서가 각각 병렬로 접속되는 회로로 구성되는 A/D 컨버터가 제공된다.

公开(公告)号：KR101887857B1

公开(公告)日：2018-08-14

申请号：KR1020170113703

申请日：2017-09-06

Applicant: 한국전력공사

Inventor： 노순철 ,  최정호 ,  민병문 ,  박은실 ,  윤여국

IPC: H03M1/20 ,  G01R31/12 ,  H03M1/12

CPC classification number: H03M1/202 ,  G01R13/0272 ,  G01R31/12 ,  H03M1/1245 ,  H03M2201/194 ,  H03M2201/6185

Abstract: 신호변환기, 이를이용한부분방전진단장치및 부분방전진단시뮬레이션장치가개시된다. 본발명의신호변환기는부분방전(PD, partial discharge) 신호를신호처리하여생성된 64 샘플링데이터에서인접한 2개의샘플링데이터사이를선형보간하여선형보간값을생성하는보간부; 및상기보간부에의해생성된선형보간값을이용하여인접한 2개의샘플링데이터사이의표준샘플링데이터를검출하는데이터검출부를포함하는것을특징으로한다.

公开(公告)号：KR101379301B1

公开(公告)日：2014-03-28

申请号：KR1020130017372

申请日：2013-02-19

Applicant: 주식회사 아진엑스텍

Inventor： 하상민 ,  원종백 ,  김창호 ,  최성혁 ,  이상태

IPC: H03M1/66

CPC classification number: H03M1/661 ,  H03M1/662 ,  H03M2201/6185 ,  H03M2201/625

Abstract: The present invention relates to a high-resolution digital-to-analog converter and a control method therefor. More particularly, the present invention relates to a digital-to-analog converter which increases a resolution using a interpolation method without using analog signal synthesis and a control method therefor. A method for generating high-resolution analog signals which relates to an embodiment of the present invention includes: a step of inputting first digital information; a step of shifting a bit of the first digital information by a predetermined bit; a step of moving the shifted first digital information to a first digital-to-analog converter (DAC) register; a step of inputting second digital information; a step of moving the shifted first digital information to a second DAC register, shifting the second digital information by the predetermined bit and moving the shifted second digital information to the first DAC register according to a synchronous signal; a step of inputting third digital information; a step of extracting the third digital information shifted by the predetermined bit using the first digital information, second digital information, shifted first digital information, shifted second digital information and interpolation method; and a step of outputting the generated analog information using the shifted third digital information. [Reference numerals] (AA) Start; (BB) End; (S100) Step of inputting first digital information of a predetermined bit; (S200) Step of shifting bit of the first digital information; (S300) Step of moving the shifted first digital information to a first DAC register; (S400) Step of moving the shifted first digital information to a second DAC register, shifting the second digital information by the predetermined bit and moving the shifted second digital information to the first DAC register according to a synchronous signal; (S500) Step of moving the shifted first digital information to a third DAC register, moving the shifted second digital information to the second DAC register, shifting third digital information and moving the shifted third digital information to the first DAC register; (S600) Step of obtaining output information having a higher resolution using the first, second, third digital information and the shifted first, second and third digital information; (S700) Step of outputting analog information using the output information

Abstract translation: 本发明涉及一种高分辨率数模转换器及其控制方法。 更具体地说，本发明涉及使用不使用模拟信号合成的内插方法提高分辨率的数/模转换器及其控制方法。 一种与本发明实施例相关的高分辨率模拟信号的产生方法，包括：输入第一数字信息的步骤; 将第一数字信息的一位移位预定位的步骤; 将移位的第一数字信息移动到第一数模转换器（DAC）寄存器的步骤; 输入第二数字信息的步骤; 将移位的第一数字信息移动到第二DAC寄存器，将第二数字信息移位预定位并根据同步信号将移位的第二数字信息移动到第一DAC寄存器的步骤; 输入第三数字信息的步骤; 使用第一数字信息，第二数字信息，移位的第一数字信息，移位的第二数字信息和插值方法提取由预定位移位的第三数字信息的步骤; 以及使用所移动的第三数字信息输出所生成的模拟信息的步骤。 （附图标记）（AA）开始; （BB）结束; （S100）输入预定位的第一数字信息的步骤; （S200）移位第一数字信息的位的步骤; （S300）将移位的第一数字信息移动到第一DAC寄存器的步骤; （S400）将移位的第一数字信息移动到第二DAC寄存器，将第二数字信息移位预定位并根据同步信号将移位的第二数字信息移动到第一DAC寄存器的步骤; （S500）将移位的第一数字信息移动到第三DAC寄存器，将移位的第二数字信息移动到第二DAC寄存器，移位第三数字信息并将移位的第三数字信息移动到第一DAC寄存器的步骤; （S600）使用第一，第二，第三数字信息和移位的第一，第二和第三数字信息获得具有较高分辨率的输出信息的步骤; （S700）使用输出信息输出模拟信息的步骤

公开(公告)号：KR101291341B1

公开(公告)日：2013-07-30

申请号：KR1020130001713

申请日：2013-01-07

Applicant: 주식회사 하이드로넷

Inventor： 임우석 ,  김상훈 ,  이준형

IPC: H03M1/12

CPC classification number: H03M1/20 ,  H03M1/123 ,  H03M1/361 ,  H03M2201/194 ,  H03M2201/2216 ,  H03M2201/6185 ,  H03M2201/625

Abstract: PURPOSE: A resolution improving device and a method thereof using an analog to digital converter port inside a MCU are provided to improve the resolution of an analog signals inputted from outside. CONSTITUTION: A resolution improving device of an analog to digital converter (ADC) comprises a bisectional unit (110), an adding device (120), and a MCU (130). The bisectional part divides an analog input signal into 2 halves for outputting the signal of a sub part. The adding device adds the analog input signal to the signal of the sub part which is outputted from the bisectional part for outputting. The MCU receives the analog input signal through a first ADC port and receives the main part signal of the signal divided into 2 halves through a second ADC port or an input and output port. The MCU converts the main part signal into a digital signal when a signal is inputted through the input and output port and assigns 1 to an additional bit above the most significant bit for outputting. The MCU converts the analog signal into the digital signal when a signal is not inputted through the input and output port and assigns 0 to the additional bit above the most significant bit for outputting. [Reference numerals] (110) Bisection of a signal; (120) Adding device; (AA) Input signal; (BB) Upper signal of the bisectional signal

Abstract translation: 目的：提供一种分辨率改进装置及其在MCU内使用模数转换器端口的方法，以提高从外部输入的模拟信号的分辨率。 构成：模数转换器（ADC）的分辨率改善装置包括二分单元（110），加法装置（120）和MCU（130）。 二等分部分将模拟输入信号分成两半，用于输出子部分的信号。 添加装置将模拟输入信号添加到从二分割部分输出的子部分的信号以进行输出。 MCU通过第一个ADC端口接收模拟输入信号，并通过第二个ADC端口或输入和输出端口将信号的主要部分信号分为两半。 当通过输入和输出端口输入信号时，MCU将主要部分信号转换为数字信号，并将1分配给高于最高有效位以用于输出。 当信号不通过输入和输出端口输入时，MCU将模拟信号转换为数字信号，并将0分配给最高有效位以上的附加位进行输出。 （附图标记）（110）信号的二等分; （120）添加设备; （AA）输入信号; （BB）二分信号的上位信号

公开(公告)号：KR1020070076111A

公开(公告)日：2007-07-24

申请号：KR1020060005123

申请日：2006-01-17

Applicant: 엘지전자 주식회사

Inventor： 김세원 ,  김상진

IPC: H03M1/12

CPC classification number: H03M1/203 ,  H03M1/123 ,  H03M2201/1172 ,  H03M2201/2216 ,  H03M2201/6185 ,  H03M2201/625

Abstract: A multi channel analog-digital converting apparatus is provided to reduce the size of apparatus and cost by forming a channel group composed of a sampling switch with low resolution and a channel group composed of a sampling switch with high resolution. A multi channel analog-digital converting apparatus includes a first channel group(10), a second channel group(20), and a group sampling switch(30). The first channel group(10) is composed of sampling switches of a predetermined number of channels having first resolution. The second channel group(20) is composed of sampling switches of a predetermined number of channels having second resolution. One side of the group sampling switch(30) is connected with the output of the second channel group(20), and the other side thereof is connected with the output of the first channel group(10).

Abstract translation: 提供一种多通道模拟数字转换装置，通过形成由低分辨率的采样开关构成的通道组和由高分辨率的采样开关组成的通道组来减小设备的尺寸和成本。 多通道模拟数字转换装置包括第一通道组（10），第二通道组（20）和组采样开关（30）。 第一通道组（10）由具有第一分辨率的预定数量的通道的采样开关组成。 第二通道组（20）由具有第二分辨率的预定数量的通道的采样开关组成。 组采样开关（30）的一侧与第二通道组（20）的输出端连接，另一侧与第一通道组（10）的输出端连接。

公开(公告)号：KR1020000027231A

公开(公告)日：2000-05-15

申请号：KR1019980045127

申请日：1998-10-27

Applicant: 에스케이하이닉스 주식회사

Inventor： 김경면

IPC: H03M1/00

CPC classification number: H03M1/002 ,  H03M1/141 ,  H03M1/202 ,  H03M1/366 ,  H03M2201/6185 ,  H03M2201/62

Abstract: PURPOSE: A folding interpolation analog-digital converter is provided to process signals in a current mode by using a transistor and a resistor only without changing the conventional reference digital CMOS process. CONSTITUTION: The folding interpolation analog-digital converter of high speed and low electric power comprises a plurality of folding sections (1¯4) for receiving and pre-processing an analog signal (Ain) into folding signals of a sinewave having multi-cross points to output as a pair of positive and negative waves, an interpolation section (5) for outputting extra folding signals having cross points of even intervals from the folding signals generated from the two adjacent folding sections of the folding sections (1¯4), a comparison section (6) for comparing the pair of folding signals of the interpolation section (5) with the reference signal to output a lower-leveled signal, an upper-bit AD converting section (7) for comparing the analog signal (Ain) with the reference signal to output an upper-bit signal, a delayed time error correction section (8) for detecting a delay difference between the lower-bit signal outputted from the comparison section (6) and the output signals of the upper-bit AD converting section (7), and a digital encoder (9) for outputting a digital signal (Dout) encoded by receiving the output signal of the comparison section (6).

Abstract translation: 目的：提供折叠插补模数转换器，通过仅使用晶体管和电阻来处理电流模式下的信号，而不改变传统的参考数字CMOS工艺。 构成：高速和低功率的折叠插补模拟数字转换器包括多个折叠部分（1〜4），用于将模拟信号（Ain）预处理成具有多交叉点的正弦波的折叠信号 作为一对正和负波输出，用于从折叠部分（1〜4）的两个相邻折叠部分产生的折叠信号中输出具有偶数间隔交叉点的额外折叠信号的插值部分（5） 比较部分（6），用于将插值部分（5）的折叠信号对与参考信号进行比较以输出较低级别的信号;高位AD转换部分（7），用于将模拟信号（Ain）与 输出高位信号的参考信号，用于检测从比较部分（6）输出的低位信号与输出信号之间的延迟差的延迟时间误差校正部分（8） e高位AD转换部分（7）和用于输出通过接收比较部分（6）的输出信号编码的数字信号（Dout）的数字编码器（9）。