公开(公告)号：KR1020080018554A

公开(公告)日：2008-02-28

申请号：KR1020060080826

申请日：2006-08-25

Applicant: 고려대학교 산학협력단

Inventor： 정해영 ,  김수원

IPC: H03M1/12

CPC classification number: H03M1/361 ,  H03M1/202 ,  H03M2201/1172 ,  H03M2201/194 ,  H03M2201/2216

Abstract: An analog to digital converting apparatus using a digital control comparator, a method thereof, and a pacemaker having the same are provided to reliably realize less power consumption by selectively operating the digital control comparators by bits. An analog to digital converting apparatus includes a plurality of digital control comparators(511~519), a digital to analog converter(520), and a successive approximation logic circuit(530). The digital control comparators sequentially generate bit values from an MSB(Most Significant Bit) by comparing input voltage(Vin) with reference voltages(Vref). The digital to analog converter generates the reference voltages applied to the comparators according to the generated bit values. The successive approximation logic circuit selects the comparator to generate the bit value of the adjacent bit according to the generated bit values, turns on the comparator, and performs a binary search.

Abstract translation: 提供了使用数字控制比较器的模数转换装置，其方法和具有该数字转换装置的起搏器，以便通过以比特选择性地操作数字控制比较器来可靠地实现更少的功耗。 模数转换装置包括多个数字控制比较器（511〜519），数模转换器（520）和逐次逼近逻辑电路（530）。 数字控制比较器通过将输入电压（Vin）与参考电压（Vref）进行比较来顺序地从MSB（最高有效位）产生位值。 数模转换器根据生成的位值产生施加到比较器的参考电压。 逐次逼近逻辑电路根据生成的位值选择比较器以产生相邻位的位值，打开比较器，并执行二进制搜索。

公开(公告)号：KR1020070076111A

公开(公告)日：2007-07-24

申请号：KR1020060005123

申请日：2006-01-17

Applicant: 엘지전자 주식회사

Inventor： 김세원 ,  김상진

IPC: H03M1/12

CPC classification number: H03M1/203 ,  H03M1/123 ,  H03M2201/1172 ,  H03M2201/2216 ,  H03M2201/6185 ,  H03M2201/625

Abstract: A multi channel analog-digital converting apparatus is provided to reduce the size of apparatus and cost by forming a channel group composed of a sampling switch with low resolution and a channel group composed of a sampling switch with high resolution. A multi channel analog-digital converting apparatus includes a first channel group(10), a second channel group(20), and a group sampling switch(30). The first channel group(10) is composed of sampling switches of a predetermined number of channels having first resolution. The second channel group(20) is composed of sampling switches of a predetermined number of channels having second resolution. One side of the group sampling switch(30) is connected with the output of the second channel group(20), and the other side thereof is connected with the output of the first channel group(10).

Abstract translation: 提供一种多通道模拟数字转换装置，通过形成由低分辨率的采样开关构成的通道组和由高分辨率的采样开关组成的通道组来减小设备的尺寸和成本。 多通道模拟数字转换装置包括第一通道组（10），第二通道组（20）和组采样开关（30）。 第一通道组（10）由具有第一分辨率的预定数量的通道的采样开关组成。 第二通道组（20）由具有第二分辨率的预定数量的通道的采样开关组成。 组采样开关（30）的一侧与第二通道组（20）的输出端连接，另一侧与第一通道组（10）的输出端连接。

公开(公告)号：KR1020090061507A

公开(公告)日：2009-06-16

申请号：KR1020070128534

申请日：2007-12-11

Applicant: 한양대학교 산학협력단

Inventor： 유창식 ,  조준기 ,  박재우 ,  신성철

IPC: H03M1/12

CPC classification number: H03M1/502 ,  H03M1/002 ,  H03M1/1205 ,  H03M1/362 ,  H03M2201/1172 ,  H03M2201/2216 ,  H03M2201/2372 ,  H03M2201/322 ,  H03M2201/61

Abstract: An analog to digital converter and an analog to digital converting method are provided to reduce power consumption and a chip size in comparison with the analog to digital converter comprised of a plurality of comparators comprised of pre-amplifiers. A reference voltage generator(10) generates a plurality of different reference voltages. A delay unit(20) changes a size of an analog input signal and the size and difference of a plurality of reference voltages into the delay time difference of an inputted clock. A phase detector(30) detects the delay time difference of the clock and generates the detection signal. A code generator(100) receives the detection signal and converts the detection signal into an N bit digital signal which increases as the analog input signal increases. The delay unit includes a first delay cell and a second delay cell. The first delay cell receives the clock and delays the clock as much as the first delay time according to the analog input signal. The second delay cell receives the clock and delays the clock as much as the second delay time according to the one reference voltage among the plurality of reference voltages.

Abstract translation: 与由前置放大器组成的多个比较器组成的模数转换器相比，提供了模数转换器和模数转换方法来降低功耗和芯片尺寸。 参考电压发生器（10）产生多个不同的参考电压。 延迟单元（20）将模拟输入信号的大小和多个参考电压的大小和差异改变为输入时钟的延迟时间差。 相位检测器（30）检测时钟的延迟时间差并产生检测信号。 代码生成器（100）接收检测信号，并将检测信号转换成随着模拟输入信号增加而增加的N位数字信号。 延迟单元包括第一延迟单元和第二延迟单元。 第一延迟单元接收时钟，并根据模拟输入信号将时钟延迟到第一延迟时间。 第二延迟单元接收时钟，并根据多个参考电压中的一个参考电压将时钟延迟多达第二延迟时间。

公开(公告)号：KR101811402B1

公开(公告)日：2017-12-21

申请号：KR1020160159384

申请日：2016-11-28

Applicant: 금오공과대학교 산학협력단 ,  (주)탑이엔씨건축사사무소

Inventor： 채석 ,  신수용 ,  이말숙

IPC: G08B25/01 ,  H03M1/34

CPC classification number: G08B17/06 ,  G08B25/018 ,  H03M1/34 ,  H03M2201/1172 ,  H03M2201/194

Abstract: 디지털아날로그변환부로제어되는전압제어전류원을이용한주소형화재감지장치는, 복수의스위치각각의전기적인연결상태에대응하는주소코드값을생성하는주소설정부; 상기주소코드값에대응하는전압레벨을갖는기준전압을생성하는디지털아날로그변환부; 및화재감지센서가액티브되었을때, 상기기준전압의제어에따라상기기준전압의전압레벨에대응하는전류값을갖는화재감지정전류를전원라인으로구동하는정전류원회로부;를포함한다.

Abstract translation: 一种使用由数模转换器控制的电压控制电流源的地址型火灾感测装置包括：地址设置单元，用于生成与多个开关中的每个开关的电连接状态对应的地址代码值; 一种用于产生具有对应于地址码值的电压电平的参考电压的数字 - 模拟转换器; 以及恒流电路单元，用于当火情检测传感器被激活时根据参考电压的控制将具有与参考电压的电压电平相对应的电流值的火情检测恒定电流驱动到电源线。

公开(公告)号：KR1020080102561A

公开(公告)日：2008-11-26

申请号：KR1020070049166

申请日：2007-05-21

Applicant: 삼성전자주식회사 ,  재단법인서울대학교산학협력재단

Inventor： 김수환 ,  양한 ,  우종관

IPC: H03M1/12

CPC classification number: H03M1/361 ,  H03M1/002 ,  H03M2201/1172 ,  H03M2201/2216 ,  H03M2201/93

Abstract: A signal converter and a method for converting a signal reduce power consumption and a layout area by applying a sharing technique and a switching technique together. A signal converter(100) includes a first amplifier always maintaining the active state, and a third amplifier maintaining the active state in a first phase and a second amplifier maintaining the active state in a second phase. While a plurality of first capacitors(C1) sample the input signal in the first phase, the serially connected first amplifier and the third amplifier amplify the voltage generated by the first voltage set. While a plurality of second capacitors(C2) sample the output voltage of the second amplifier in the second phase, the serially connected first amplifier and the second amplifier amplify the voltage generated by the second voltage set.

Abstract translation: 信号转换器和用于转换信号的方法通过共享技术和切换技术共同地降低功耗和布局面积。 信号转换器（100）包括总是维持有效状态的第一放大器和保持第一相位中的有效状态的第三放大器和保持第二阶段的激活状态的第二放大器。 当多个第一电容器（C1）在第一相中对输入信号进行采样时，串联的第一放大器和第三放大器放大由第一电压组产生的电压。 当多个第二电容器（C2）在第二相中对第二放大器的输出电压进行采样时，串联的第一放大器和第二放大器放大由第二电压组产生的电压。

公开(公告)号：KR1020060122190A

公开(公告)日：2006-11-30

申请号：KR1020050044240

申请日：2005-05-25

Applicant: 주식회사 에이티앤에스

Inventor： 오정호

IPC: H03M1/10

CPC classification number: H03M1/123 ,  H03M1/129 ,  H03M1/188 ,  H03M2201/1172 ,  H03M2201/196

Abstract: An AD converting device is provided to convert a wide band analog signal into a digital signal without quantization distortion. In an AD converting device, an analog signal dividing unit(300) divides a frequency band with an input analogue signal into more than two sub bands. A sub band AD converting unit(100-1 to 100-N) AD converts a signal of each sub band divided by the analog signal dividing unit(300). A digital signal combining unit(200) combines output digital signals of the sub band AD converting unit(100-1 to 100-N) into one.

Abstract translation: 提供AD转换装置以将宽带模拟信号转换成数字信号而不产生量化失真。 在AD转换装置中，模拟信号分割单元（300）将具有输入模拟信号的频带划分成多于两个子带。 子频带AD转换单元（100-1至100-N）AD转换由模拟信号分割单元（300）划分的每个子带的信号。 数字信号组合单元（200）将子带AD转换单元（100-1至100-N）的输出数字信号组合成一个。