公开(公告)号：WO2007015915A1

公开(公告)日：2007-02-08

申请号：PCT/US2006/028092

申请日：2006-07-19

Applicant: ATI TECHNOLOGIES, INC. ,  LEE, Edward ,  BOMDICA, Arvind ,  CHEN, Lin ,  GAUTHIER, Claude ,  HUYNH, Sam ,  NG, Hiok-Tiaq ,  LING, John ,  HO, Jennifer ,  M.K., Siji ,  YEE, Gin ,  MACRI, Joseph

Inventor： LEE, Edward ,  BOMDICA, Arvind ,  CHEN, Lin ,  GAUTHIER, Claude ,  HUYNH, Sam ,  NG, Hiok-Tiaq ,  LING, John ,  HO, Jennifer ,  M.K., Siji ,  YEE, Gin ,  MACRI, Joseph

IPC: H04L7/033

CPC classification number: H03L7/0814 ,  H03L7/07 ,  H03L7/0805 ,  H04L7/0004 ,  H04L7/0037 ,  H04L7/0337

Abstract: An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.

Abstract translation: 描述了用于位移校正的IO方法和系统。 实施例包括具有在其间传送数据的多个组件的计算机系统。 在一个实施例中，系统组件从发送组件接收正向选通信号和多个数据位信号。 接收组件包括可选择对准正向选通采样时钟的正向选通时钟恢复电路，以便提高采样精度。 接收组件还包括至少一个数据比特时钟恢复电路，可配置为对准数据比特采样时钟，以便提高采样精度，并接收来自正向选通时钟恢复电路的信号，使得数据比特采样时钟跟踪 系统运行期间的正向选通采样时钟。

公开(公告)号：WO2006126092A2

公开(公告)日：2006-11-30

申请号：PCT/IB2006/001468

申请日：2006-05-26

Applicant: ATI TECHNOLOGIES, INC. ,  ATI INTERNATIONAL S.R.L. ,  CAMPBELL, Jon ,  RIBBLE, Maurice

Inventor： CAMPBELL, Jon ,  RIBBLE, Maurice

IPC: G06T1/20

CPC classification number: G06F15/16 ,  G06T1/20 ,  G06T15/005

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.

Abstract translation: 提供了处理数据的系统和方法。 系统和方法包括每个耦合以接收命令和数据的多个处理器，其中命令和/或数据对应于包括多个像素的视频帧。 互连模块被耦合以接收对应于来自每个处理器的帧的处理数据。 互连模块通过使用至少一个平衡点划分第一帧的像素来将第一帧划分成多个帧部分。 互连模块动态地确定在处理命令和/或一个或多个后续帧的数据期间最小化处理器的工作量之间的平衡点的位置。

公开(公告)号：WO2006048695A1

公开(公告)日：2006-05-11

申请号：PCT/IB2004/003568

申请日：2004-11-01

Applicant: ATI TECHNOLOGIES, INC. ,  ATI INTERNATIONAL, SRL ,  KOURAMANIS, Ioannis ,  ALEKSIC, Milivoje

Inventor： KOURAMANIS, Ioannis ,  ALEKSIC, Milivoje

IPC: G06T9/00

CPC classification number: H04N19/59 ,  H04N19/126 ,  H04N19/15 ,  H04N19/172 ,  H04N19/194

Abstract: In accordance with an aspect of the present invention, the compressed size of an image to be captured is predicted using an earlier predictor image at an image sensor. Based on the prediction, one or more adjusted compression parameters are assessed so that the image to be captured, when compressed using the adjusted parameters will likely fit within an image buffer of finite size. Conveniently, the earlier image typically acts as a good predictor of the image to be captured.

Abstract translation: 根据本发明的一个方面，使用图像传感器上的较早预测图像来预测要捕获的图像的压缩大小。 基于预测，评估一个或多个经调整的压缩参数，使得当使用经调整的参数进行压缩时要捕获的图像将可能适合有限大小的图像缓冲器。 方便地，早期的图像通常用作要捕获的图像的良好预测器。

公开(公告)号：WO2005029407A1

公开(公告)日：2005-03-31

申请号：PCT/IB2004/003064

申请日：2004-09-20

Applicant: ATI TECHNOLOGIES, INC. ,  ATI INTERNATIONAL, SRL

Inventor： KOURAMANIS, Ioannis ,  SMIRNOV, Maxim ,  ALEKSIC, Milivoje

IPC: G06T1/60

CPC classification number: H04N5/772 ,  G09G5/363 ,  G09G5/39 ,  H04N5/85 ,  H04N5/907 ,  H04N9/7921 ,  H04N9/8042 ,  H04N9/8047

Abstract: The present invention provides a method and apparatus for image processing using a graphics processor in a handheld device including a first memory device receiving a video input signal containing encoded video frame having a plurality of portions of encoded video frame data. The first memory device has a storage capacity less than all of the plurality portions of the encoded video frame data. The method and apparatus further includes the graphics processor coupled to the first memory device, wherein the graphics processor receives the first portion of the encoded video frame data and generates a first graphics portion. A second memory device receives the first graphics portion and stores the first graphics portion therein. As such, the encoded video frame is processed on a portion-by-portion basis using the first memory device and the second memory device in conjunction with the graphics processor.

Abstract translation: 本发明提供了一种用于在手持设备中使用图形处理器进行图像处理的方法和装置，该手持设备包括接收包含编码视频帧的视频输入信号的第一存储器件，该编码视频帧具有编码视频帧数据的多个部分。 第一存储器件具有小于编码视频帧数据的多个部分的存储容量。 该方法和装置还包括耦合到第一存储器件的图形处理器，其中图形处理器接收编码视频帧数据的第一部分并产生第一图形部分。 第二存储器装置接收第一图形部分并将第一图形部分存储在其中。 这样，使用第一存储器设备和第二存储器设备结合图形处理器，逐个部分地处理编码视频帧。

公开(公告)号：WO2008021489A3

公开(公告)日：2008-05-29

申请号：PCT/US2007018245

申请日：2007-08-17

Applicant: ATI TECHNOLOGIES INC ,  TAYLOR STUART A ,  MA VICTOR ,  PATEL BHARAT

Inventor： TAYLOR STUART A ,  MA VICTOR ,  PATEL BHARAT

IPC: G06F17/50 ,  H01L23/52

CPC classification number: G06F17/5045 ,  G06F2217/84

Abstract: An integrated circuit (IC) chip having repeaters for propagating signals along relatively long wires that extend between and among lower-level physical blocks of the IC chip, wherein the repeaters are implemented as clocked flip-flops (or "repeater flops"). A method for automatically inserting and allocating such repeater flops during the logical and physical design of the IC chip is also provided.

Abstract translation: 一种集成电路（IC）芯片，其具有用于沿着在IC芯片的下级物理块之间延伸的较长导线传播信号的中继器，其中中继器被实现为时钟触发器（或“中继器”）。 还提供了在IC芯片的逻辑和物理设计期间自动插入和分配这种中继器的方法。

公开(公告)号：WO2008027413A2

公开(公告)日：2008-03-06

申请号：PCT/US2007018965

申请日：2007-08-29

Applicant: ATI TECHNOLOGIES INC ,  IOURCHA KONSTANTINE ,  POMIANOWSKI ANDREW S C

Inventor： IOURCHA KONSTANTINE ,  POMIANOWSKI ANDREW S C

IPC: H04N7/26 ,  G06T9/00

CPC classification number: H04N19/426 ,  G06T9/00 ,  H04N19/119 ,  H04N19/154 ,  H04N19/176 ,  H04N19/182 ,  H04N19/46 ,  H04N19/54 ,  H04N19/60 ,  H04N19/96

Abstract: A texture compression method is described. The method comprises splitting an original texture having a plurality of pixels into original blocks of pixels. Then, for each of the original blocks of pixels, a partition is identified that has one or more disjoint subsets of pixels whose union is the original block of pixels. The original block of pixels is further subdivided into one or more subsets according to the identified partition. Finally, each subset is independently compressed to form a compressed texture block.

Abstract translation: 描述纹理压缩方法。 该方法包括将具有多个像素的原始纹理分解为原始的像素块。 然后，对于每个原始的像素块，识别出具有一个或多个不相交像素子集的分区，其并集是原始的像素块。 根据所识别的分区，原始像素块被进一步细分成一个或多个子集。 最后，每个子集被独立地压缩以形成压缩的纹理块。

公开(公告)号：WO2008021489A2

公开(公告)日：2008-02-21

申请号：PCT/US2007/018245

申请日：2007-08-17

Applicant: ATI TECHNOLOGIES INC. ,  TAYLOR, Stuart, A. ,  MA, Victor ,  PATEL, Bharat

Inventor： TAYLOR, Stuart, A. ,  MA, Victor ,  PATEL, Bharat

IPC: G06F17/50 ,  H01L23/52

CPC classification number: G06F17/5045 ,  G06F2217/84

Abstract: An integrated circuit (IC) chip having repeaters for propagating signals along relatively long wires that extend between and among lower-level physical blocks of the IC chip, wherein the repeaters are implemented as clocked flip-flops (or "repeater flops"). A method for automatically inserting and allocating such repeater flops during the logical and physical design of the IC chip is also provided.

Abstract translation: 具有转发器的集成电路（IC）芯片用于沿着在IC芯片的较低级物理块之间延伸的较长导线传播信号，其中转发器被实现为时钟触发器（ 或“中继器触发器”）。 还提供了在IC芯片的逻辑和物理设计期间自动插入和分配这种中继器触发器的方法。

公开(公告)号：WO2007072211A3

公开(公告)日：2007-10-04

申请号：PCT/IB2006003814

申请日：2006-12-21

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  STRASSER DAVID A

Inventor： STRASSER DAVID A

IPC: H04N5/00 ,  H04N7/16 ,  H04N7/24

CPC classification number: H04N21/4623 ,  H04N21/4143 ,  H04N21/418 ,  H04N21/4181 ,  H04N21/4183 ,  H04N21/4305 ,  H04N21/440218 ,  H04N21/4405 ,  H04N21/4621

Abstract: To receive new services including audio or video content for presentation by a cable-compatible digital television or other digital audio/video receiver, a module may be connected to the HOST-POD interface of the digital television. The module has a receiver for receiving audio or video content in a first compression format, a transcoder for converting said audio or video content from the first compression format into a second, different compression format, and a controller for transmitting the audio or visual content in the second compression format to the digital television over a HOST-POD interface. By using such a module, front-end components of the digital television may be bypassed while back-end components may be utilized to decompress and present the content. The module may be a PC card or smart card for example.

Abstract translation: 为了接收新的服务，包括音频或视频内容，用于由电缆兼容的数字电视或其他数字音频/视频接收机呈现，模块可以连接到数字电视的HOST-POD接口。 该模块具有用于以第一压缩格式接收音频或视频内容的接收器，用于将所述音频或视频内容从第一压缩格式转换成第二不同压缩格式的代码转换器，以及用于将音频或视频内容传输到 通过HOST-POD接口向数字电视提供第二种压缩格式。 通过使用这样的模块，数字电视的前端组件可以被旁路，而后端组件可以用于解压缩并呈现内容。 该模块可以是例如PC卡或智能卡。

公开(公告)号：WO2007093906A1

公开(公告)日：2007-08-23

申请号：PCT/IB2007/000381

申请日：2007-02-16

Applicant: ATI TECHNOLOGIES, INC ,  ATI INTERNATIONAL SRL ,  MACRI, Joseph ,  MOREIN, Stephen, L. ,  LEE, Edward (Ming-Ju) ,  CHEN, Lin

Inventor： MACRI, Joseph ,  MOREIN, Stephen, L. ,  LEE, Edward (Ming-Ju) ,  CHEN, Lin

IPC: H04L25/49 ,  G06F13/42

CPC classification number: H04L25/4915 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0814 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0337

Abstract: A dynamic bus inversion (DBI) method and system are described. In various embodiments, a transmitter transmits data over a multi-bit high-speed bus to a receiver. In an embodiment, the transmitter determines whether to invert the bus based on the number of data bits that will be transitioning to a new value. If it is determined that the bus is to be inverted, the transmitter encodes a DBI signal on a shared line of the bus. In an embodiment, the shared line is used for different purposes at different times, obviating the need for a dedicated line or pin for the encoded DBI signal. The receiver receives and decodes the DBI signal and, in response, appropriately decodes the received data.

Abstract translation: 描述了动态总线反演（DBI）方法和系统。 在各种实施例中，发射机通过多比特高速总线向接收机发送数据。 在一个实施例中，发射机基于将要转换到新值的数据比特数来确定是否反转总线。 如果确定总线被反相，则发送器对总线的共享线路上的DBI信号进行编码。 在一个实施例中，共享线路在不同时间用于不同的目的，从而避免了对编码的DBI信号的专用线路或引脚的需要。 接收器接收并解码DBI信号，并且作为响应，适当地解码所接收的数据。

公开(公告)号：WO2007085963A2

公开(公告)日：2007-08-02

申请号：PCT/IB2007000260

申请日：2007-01-30

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  SAGALOVITCH SERGUEI ,  CHAN HING PONG ,  YURIN ALEXEI

Inventor： SAGALOVITCH SERGUEI ,  CHAN HING PONG ,  YURIN ALEXEI

CPC classification number: G06F9/4881 ,  G06F9/485

Abstract: To provide for the processing of priority data elements between a host processor and a co- processor that exchange such data elements using a queue, the host processor determines a priority of a data element received from an application. If the priority is higher than a lowest possible priority value, at least one lower priority data element within the queue may be identified and modified thereby temporarily removing it from the queue. When the priority data element is written into the queue a query packet is included that will cause the co-processor to return information regarding a last executed queued data element. Based on the returned information, the host processor can determine one or more unmodified data elements (uniquely corresponding to the one or more modified queued data elements) to be written into the queue in accordance with a sequence of the previously modified queued data elements.

Abstract translation: 为了提供在主机处理器和使用队列交换这样的数据元素的协处理器之间的优先级数据元素的处理，主处理器确定从应用接收的数据元素的优先级。 如果优先级高于最低可能的优先级值，则可以识别和修改队列内的至少一个较低优先级的数据元素，从而将其临时从队列中移除。 当优先级数据元素被写入队列时，包括查询分组，这将使协处理器返回关于最后执行的排队数据元素的信息。 基于返回的信息，主机处理器可以根据先前修改的排队数据元素的顺序来确定要写入队列的一个或多个未修改数据元素（唯一对应于一个或多个修改后的排队数据元素）。