公开(公告)号：WO1993013478A1

公开(公告)日：1993-07-08

申请号：PCT/US1992010953

申请日：1992-12-18

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  NEUFELD, E., David

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F3/0601 ,  G06F2003/0692 ,  G06F2211/1033 ,  G11B20/1833

Abstract: A method and apparatus for improving disk performance during partial stripe write operations in a computer system having a disk array subsystem utilizing parity fault tolerance technique. When a partial stripe write generation is begun, the method determines if the area or stripe where the write is to occur is unused space in the file system. If not, the partial stripe write operation is performed using a preceding read operation to read the current data and parity information from the disk as would normally be done. However, if the write area is unused space in the file system, then the contents of the data stripe do not need to be preserved. In this instance, the partial stripe write operation can be performed without any preceding read operations. By obviating the necessity of a preceding read operation, much of the performance penalty of doing a partial stripe write in the case where the rest of the data stripe does not need to be preserved is removed.

Abstract translation: 一种用于在具有使用奇偶校验容错技术的磁盘阵列子系统的计算机系统中的部分条带写入操作期间提高磁盘性能的方法和装置。 当开始部分条带写入生成时，该方法确定要发生写入的区域或条带是文件系统中的未使用空间。 如果不是，则使用前面的读取操作来执行部分条带写入操作，以如通常所做的那样从盘读取当前数据和奇偶校验信息。 但是，如果写入区域是文件系统中未使用的空间，则不需要保留数据条带的内容。 在这种情况下，可以在没有任何先前的读取操作的情况下执行部分条带写入操作。 通过消除前面的读取操作的必要性，消除了在不需要保留数据条带的其余部分的情况下进行部分条带写入的许多性能损失。

公开(公告)号：WO1993012480A1

公开(公告)日：1993-06-24

申请号：PCT/US1992010798

申请日：1992-12-14

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  ATKINSON, Lee, W.

IPC: G06F01/32

CPC classification number: G06F1/3215 ,  G06F1/3203 ,  G06F11/3409 ,  G06F11/3423 ,  G06F12/0802 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885 ,  Y02D10/126 ,  Y02D10/34

Abstract: A battery powered computer system determines when the system is not in use by monitoring various events associated with the operation of the system. The system preferably monitors the number of cache read misses and write operations, i.e., the cache hit rate, and reduces the system clock frequency when the cache hit rate rises above a certain level. When the cache hit rate is above a certain level, then it can be assumed that the processor is executing a tight loop, such as when the processor is waiting for a key to be pressed and then the frequency can be reduced without affecting system performance. Alternatively, the apparatus monitors the occurrence of memory page misses, I/O write cycles or other events to determine the level of activity of the computer system.

Abstract translation: 电池供电的计算机系统通过监视与系统的操作相关联的各种事件来确定系统何时未使用。 该系统优选地监视高速缓存读取未命中和写入操作的数量，即，高速缓存命中率，并且当高速缓存命中率上升到高于某一水平时，降低系统时钟频率。 当高速缓存命中率高于一定水平时，可以假设处理器正在执行紧密循环，例如当处理器正在等待一个按键被按下时，可以在不影响系统性能的情况下降低频率。 或者，该装置监视存储器页面未命中，I / O写入周期或其他事件的发生，以确定计算机系统的活动级别。

公开(公告)号：WO1993010494A1

公开(公告)日：1993-05-27

申请号：PCT/US1992009875

申请日：1992-11-16

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  FAIRCHILD, Steven, E. ,  GEROCHE, Michael, R. ,  LUNDGREEN, Mark, T. ,  KLINGSPORN, Benny, J.

IPC: G06F11/26

CPC classification number: G06F11/2221 ,  G06F11/008 ,  G06F11/076 ,  G06F11/2205 ,  G06F11/3485 ,  G11B20/182

Abstract: A dynamic testing method for determining disk drive error rates based on the number of bytes which are read from a hard disk drive during test. The method identifies specific faulting disk sectors and disk error types and maintains a log of the errors. The method also accumulates the total number of bytes which have been read from the disk and determines whether the disk under test has exceeded acceptable error rates based on the number of bytes read during the test. This permits the method to identify a disk drive as having failed its test prior to completion of the full disk drive test cycle.

Abstract translation: 一种基于在测试期间从硬盘读取的字节数来确定磁盘驱动器错误率的动态测试方法。 该方法识别特定的故障磁盘扇区和磁盘错误类型，并维护错误日志。 该方法还会累积从磁盘读取的总字节数，并根据测试期间读取的字节数，确定被测磁盘是否超过可接受的错误率。 这样就可以在完成磁盘驱动器测试周期之前将该磁盘驱动器识别为未通过测试。

公开(公告)号：WO1994026525A1

公开(公告)日：1994-11-24

申请号：PCT/US1994005061

申请日：1994-05-04

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  STORTZ, James, L.

IPC: B41J02/205

CPC classification number: B41J2/2128 ,  B41J2202/10

Abstract: A spot size modulatable, drop-on-demand type ink jet printhead (2) for producing grey-scale images on a substrate. The ink jet printhead (2) includes a main body portion (14) having an ink-carrying channel (6) extending therethrough and a piezoelectric actuator (34) coupled to the ink-carrying channel (6). A spot size for droplets to form when striking the substrate after ejection from the ink-carrying channel (6) is selected and a look-up table (54) translates the selected spot size into a time period during which a voltage pulse is to be applied to the piezoelectric actuator (34) by an associated switching structure (62) to initiate application of the voltage waveform, determines whether the voltage waveform has been applied to the piezoelectric actuator (34) for the time period and terminates application of the voltage waveform upon expiration of the time period. The control circuit includes a sequencer (60) which selectively asserts or deasserts at least one control signal to the switching structure, a timer (52) which instructs the sequencer (60) to initiate application of the voltage waveform and determines time elapsed since initiating application, and a comparator (58) which compares the time period produced by the look-up table (54) and the elapsed time determined by the timer (52).

Abstract translation: 用于在基板上产生灰度图像的点尺寸可调节按需喷墨打印头（2）。 喷墨打印头（2）包括具有延伸穿过其中的墨水输送通道（6）的主体部分（14）和耦合到墨水输送通道（6）的压电致动器（34）。 选择在从墨水输送通道（6）喷射之后撞击基板时形成的液滴的光斑尺寸，并且查找表（54）将所选择的光点尺寸转换为电压脉冲将在该时间段内 通过相关联的开关结构（62）施加到压电致动器（34）以开始施加电压波形，确定电压波形是否已经施加到压电致动器（34）一段时间并终止施加电压波形 期限届满时。 所述控制电路包括定序器（60），其选择性地向所述开关结构断言或解除至少一个控制信号;定时器（52），其指示所述定序器（60）开始施加所述电压波形并确定自启动应用以来经过的时间 ，以及比较器（58），其比较由查找表（54）产生的时间周期和由定时器（52）确定的经过时间。

公开(公告)号：WO1994016379A1

公开(公告)日：1994-07-21

申请号：PCT/US1994000333

申请日：1994-01-11

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  WALKER, Richard, E.

IPC: G06F01/32

CPC classification number: G06F1/3218 ,  G09G2330/021

Abstract: A computer system has a monitor which can be powered down to conserve electrical power. The monitor has two power modes, normal power mode and low power mode. Upon receiving a signal from the CPU, the monitor switches betwen power modes.

Abstract translation: 计算机系统具有可以断电以节省电力的监视器。 显示器有两种电源模式，正常电源模式和低功耗模式。 监视器从CPU接收到信号后，会在电源模式之间切换。

公开(公告)号：WO1994008445A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009203

申请日：1993-09-24

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  GEBARA, Ghassan, R.

IPC: H05K09/00

CPC classification number: H05K1/0218 ,  H05K1/0219 ,  H05K9/0039 ,  H05K2201/093

Abstract: An EMR reduction technique using grounded conductive traces and vias circumscribing the internal planes of printed wiring boards. Conductive vias are placed in a circuitous path near the border and encircling the signal traces of each layer of a printed circuit board. The ground plane is extended to encompass and electrically ground each of the vias. For each signal plane, a conductive trace is routed and connected to each of the vias forming a grounded shield around the signal-carrying traces on the signal plane. For the power planes, a conductive trace is also provided connecting the conductive vias and forming a grounded shield around the power planes. A non-conductive path is provided between the power plane and the power plane conductive trace to electrically isolate the voltages of the power plane from the grounded conductive trace.

Abstract translation: 使用接地导电迹线和通孔限制印刷电路板的内部平面的EMR降低技术。 导电通孔放置在靠近边界的迂回路径中并且环绕印刷电路板的各层的信号迹线。 接地平面被延伸以包围和电接地每个通孔。 对于每个信号平面，导电迹线被路由并连接到在信号平面上的信号载体迹线周围形成接地屏蔽的每个通孔。 对于电源平面，还提供连接导电通孔并在电源平面周围形成接地屏蔽的导电迹线。 在电源平面和电源平面导电迹线之间提供非导电路径，以将电源平面的电压与接地的导电迹线电隔离。

公开(公告)号：WO1994008313A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009410

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  CULLEY, Paul, R. ,  LANDRY, John, A. ,  MAYER, Dale, J. ,  WANNER, Christopher, C. ,  McSWAIN, Guy, E.

IPC: G06F15/80

CPC classification number: G06F15/8015 ,  G06F13/24 ,  G06F13/32

Abstract: An arrangement of direct memory access (DMA), interrupt and timer functions in a multiprocessor computer system to allow symmetrical processing. Several functions which are considered common to all of the CPUs and those which are conveniently accessed through an expansion bus remain in a central system peripheral chip coupled to the expansion bus. These central functions include the primary portions of the DMA controller and arbitration circuitry to control access of the expansion bus. A distributed peripheral, including a programmable interrupt controller, multiprocessor interrupt logic, nonmaskable interrupt logic, local DMA logic and timer functions, is provided locally for each CPU. A bus is provided between the central and distributed peripherals to allow the central peripheral to broadcast information to the CPUs, and to provide local information from the distributed chip to the central peripheral when the local CPU is programming or accessing functions in the central peripheral.

Abstract translation: 在多处理器计算机系统中安排直接存储器访问（DMA），中断和定时器功能，以允许对称处理。 被认为是所有CPU通用的几个功能以及通过扩展总线方便地访问的那些功能保留在耦合到扩展总线的中央系统外围芯片中。 这些中心功能包括DMA控制器的主要部分和控制扩展总线访问的仲裁电路。 本地为每个CPU提供了分布式外设，包括可编程中断控制器，多处理器中断逻辑，不可屏蔽中断逻辑，本地DMA逻辑和定时器功能。 在中央和分布式外设之间提供总线，以允许中央外设向CPU广播信息，并且当本地CPU在中央外设中编程或访问功能时，将分布式芯片的本地信息提供给中央外设。

公开(公告)号：WO1994008302A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009362

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  MELO, Maria, L. ,  WOLFORD, Jeff, W. ,  MORIARTY, Michael ,  CULLEY, Paul, R. ,  SCHNELL, Arnold, T.

IPC: G06F13/36

CPC classification number: G06F13/36 ,  G06F13/362

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

Abstract translation: 用于确定多个CPU中的哪一个接收优先权以成为多处理器系统中的主机总线的总线的三个优先级方案，以及用于将控制从一个总线主机传送到另一个总线主机的仲裁方案。 每个优先排序方案优先考虑n个元素，其中总共（n / 2）x（n-1）个优先级位监视每对元素之间的相对优先级。 当与该元素相关联的n-1个优先级位中的每一个指向它时，元素接收最高优先级。 在仲裁方案中，主机总线的当前总线主机确定主机总线的控制何时发生，由优先级排列方案之一决定。 仲裁方案给予EISA总线主机，RAM刷新和DMA优先于作为总线主机的CPU，并允许临时总线主机中断当前总线主机以执行回写高速缓存干预周期。 仲裁方案还支持在尝试锁定循环时中止CPU的地址流水线，突发，拆分事务和预留。 地址流水线允许下一个总线主机在下一个总线主机的数据传输阶段开始之前断言其地址和状态信号。 拆分事务允许CPU向EISA总线发布读取，以将主机总线仲裁到另一个设备，而不需要重新仲裁主机总线来检索数据。 即使主机总线被其他设备控制，数据在空闲时也在主机总线上被断言。

公开(公告)号：WO1994008301A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009186

申请日：1993-09-24

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  TIPLEY, Roger, E. ,  MORIARTY, Michael ,  TAYLOR, Mark

IPC: G06F13/36

CPC classification number: G06F13/36 ,  G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

Abstract translation: 用于确定多个CPU中的哪一个接收优先权以成为多处理器系统中的主机总线的总线的三个优先级方案，以及用于将控制从一个总线主机传送到另一个总线主机的仲裁方案。 每个优先排序方案优先考虑n个元素，其中总共（n / 2）x（n-1）个优先级位监视每对元素之间的相对优先级。 当与该元素相关联的n-1个优先级位中的每一个指向它时，元素接收最高优先级。 在仲裁方案中，主机总线的当前总线主机确定主机总线的控制何时发生，由优先级排列方案之一决定。 仲裁方案给予EISA总线主机，RAM刷新和DMA优先于作为总线主机的CPU，并允许临时总线主机中断当前总线主机以执行回写高速缓存干预周期。 仲裁方案还支持在尝试锁定循环时中止CPU的地址流水线，突发，拆分事务和预留。 地址流水线允许下一个总线主机在下一个总线主机的数据传输阶段开始之前断言其地址和状态信号。 拆分事务允许CPU向EISA总线发布读取，以将主机总线仲裁到另一个设备，而不需要重新仲裁主机总线来检索数据。 即使主机总线被其他设备控制，数据在空闲时也在主机总线上被断言。

公开(公告)号：WO1994008300A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009411

申请日：1993-09-30

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  MAYER, Dale, J. ,  LANDRY, John, A. ,  CULLEY, Paul, R.

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: A method and apparatus which maintains strict ordering of processor cycles to guarantee that a processor write, such as an EOI instruction, is not executed to the interrupt controller prior to the interrupt request from a requesting device being cleared at the interrupt controller, thus maintaining system integrity. Interrupt controller logic is included on each respective CPU board. The processor can access the interrupt controller over a local bus without having to access the host bus or the expansion bus and thus an interrupt controller access could be completed before a previously generated I/O cycle has completed. Therefore, the apparatus which tracks expansion bus cycles and interrupt controller accesses and maintains strict ordering of these cycles to guarantee that an interrupt request is cleared at the interrupt controller prior to execution of write operation to the interrupt controller.

Abstract translation: 一种保持处理器周期的严格排序以保证在来自请求设备在中断控制器处被清除的中断请求之前不向中断控制器执行诸如EOI指令之类的处理器写入的方法和装置，因此维护系统 完整性。 中断控制器逻辑包含在每个相应的CPU板上。 处理器可以通过本地总线访问中断控制器，而无需访问主机总线或扩展总线，因此在先前生成的I / O周期完成之前可以完成中断控制器访问。 因此，跟踪扩展总线周期和中断控制器的设备访问并维护这些周期的严格排序，以保证在执行到中断控制器的写操作之前在中断控制器处清除中断请求。