公开(公告)号：WO1994008302A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009362

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  MELO, Maria, L. ,  WOLFORD, Jeff, W. ,  MORIARTY, Michael ,  CULLEY, Paul, R. ,  SCHNELL, Arnold, T.

IPC: G06F13/36

CPC classification number: G06F13/36 ,  G06F13/362

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

Abstract translation: 用于确定多个CPU中的哪一个接收优先权以成为多处理器系统中的主机总线的总线的三个优先级方案，以及用于将控制从一个总线主机传送到另一个总线主机的仲裁方案。 每个优先排序方案优先考虑n个元素，其中总共（n / 2）x（n-1）个优先级位监视每对元素之间的相对优先级。 当与该元素相关联的n-1个优先级位中的每一个指向它时，元素接收最高优先级。 在仲裁方案中，主机总线的当前总线主机确定主机总线的控制何时发生，由优先级排列方案之一决定。 仲裁方案给予EISA总线主机，RAM刷新和DMA优先于作为总线主机的CPU，并允许临时总线主机中断当前总线主机以执行回写高速缓存干预周期。 仲裁方案还支持在尝试锁定循环时中止CPU的地址流水线，突发，拆分事务和预留。 地址流水线允许下一个总线主机在下一个总线主机的数据传输阶段开始之前断言其地址和状态信号。 拆分事务允许CPU向EISA总线发布读取，以将主机总线仲裁到另一个设备，而不需要重新仲裁主机总线来检索数据。 即使主机总线被其他设备控制，数据在空闲时也在主机总线上被断言。

公开(公告)号：WO1994008301A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009186

申请日：1993-09-24

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  TIPLEY, Roger, E. ,  MORIARTY, Michael ,  TAYLOR, Mark

IPC: G06F13/36

CPC classification number: G06F13/36 ,  G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

Abstract translation: 用于确定多个CPU中的哪一个接收优先权以成为多处理器系统中的主机总线的总线的三个优先级方案，以及用于将控制从一个总线主机传送到另一个总线主机的仲裁方案。 每个优先排序方案优先考虑n个元素，其中总共（n / 2）x（n-1）个优先级位监视每对元素之间的相对优先级。 当与该元素相关联的n-1个优先级位中的每一个指向它时，元素接收最高优先级。 在仲裁方案中，主机总线的当前总线主机确定主机总线的控制何时发生，由优先级排列方案之一决定。 仲裁方案给予EISA总线主机，RAM刷新和DMA优先于作为总线主机的CPU，并允许临时总线主机中断当前总线主机以执行回写高速缓存干预周期。 仲裁方案还支持在尝试锁定循环时中止CPU的地址流水线，突发，拆分事务和预留。 地址流水线允许下一个总线主机在下一个总线主机的数据传输阶段开始之前断言其地址和状态信号。 拆分事务允许CPU向EISA总线发布读取，以将主机总线仲裁到另一个设备，而不需要重新仲裁主机总线来检索数据。 即使主机总线被其他设备控制，数据在空闲时也在主机总线上被断言。

公开(公告)号：EP0664031B1

公开(公告)日：1997-01-22

申请号：EP93924899.3

申请日：1993-09-24

Applicant: Compaq Computer Corporation

Inventor： TIPLEY, Roger, E. ,  MORIARTY, Michael ,  TAYLOR, Mark

IPC: G06F13/36 ,  G06F13/364

CPC classification number: G06F13/36 ,  G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：EP0615640B1

公开(公告)日：1998-11-25

申请号：EP93922810.2

申请日：1993-09-29

Applicant: Compaq Computer Corporation

Inventor： MELO, Maria, L. ,  WOLFORD, Jeff, W. ,  MORIARTY, Michael ,  CULLEY, Paul, R. ,  SCHNELL, Arnold, T.

IPC: G06F13/36

CPC classification number: G06F13/36 ,  G06F13/362

公开(公告)号：EP0664031A1

公开(公告)日：1995-07-26

申请号：EP93924899.0

申请日：1993-09-24

Applicant: Compaq Computer Corporation

Inventor： TIPLEY, Roger, E. ,  MORIARTY, Michael ,  TAYLOR, Mark

IPC: G06F13

CPC classification number: G06F13/36 ,  G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：EP0615640A1

公开(公告)日：1994-09-21

申请号：EP93922810.0

申请日：1993-09-29

Applicant: Compaq Computer Corporation

Inventor： MELO, Maria, L. ,  WOLFORD, Jeff, W. ,  MORIARTY, Michael ,  CULLEY, Paul, R. ,  SCHNELL, Arnold, T.

IPC: G06F13 ,  G06F15

CPC classification number: G06F13/36 ,  G06F13/362

Abstract: L'invention utilise trois programmes de classement par ordre de priorité pour déterminer laquelle de plusieurs unités centrales reçoit la priorité de devenir le processeur maître de bus d'un bus hôte dans un système à multiprocesseur, et un programme d'arbitrage pour transférer le contrôle d'un maître de bus à un autre. Chaque programme de classement par ordre de priorité classe par priorité n éléments, où un total de (n/2)x(n-1) bits de priorité permet de contrôler la priorité relative entre chaque paire d'éléments. Un élément reçoit la plus grande priorité lorsque chacun des n-1 bits de priorité associés à cet élément le désigne. Dans le programme d'arbitrage, le maître de bus effectif détermine à quel moment le transfert de contrôle du bus hôte se produit tel qu'il est régi par l'un des programmes de classement par ordre de priorité. Le programme d'arbitrage donne aux maîtres de bus EISA, à la régénération de mémoire RAM et à l'accès en mémoire direct DMA une priorité plus grande qu'aux unités centrales agissant comme maîtres de bus, et il permet à un maître de bus temporaire d'interrompre le maître de bus en cours pour effectuer un cycle d'intervention de réécriture en antémémoire. Le programme d'arbitrage permet également un traitement "pipeline" d'adresses, une transmission en salve, des transactions fractionnées et des réservations d'unités centrales avortées, lors de l'essai d'un cycle verrouillé. Le traitement "pipeline" d'adresses permet au prochain maître de bus de transmettre son adresse et les signaux d'état avant le début de la phase de transfert de données du prochain maître de bus. Les transactions fractionnées permettent à une unité centrale, ayant demandé une lecture dans le bus EISA, d'affecter après arbitrage le bus hôte à un autre dispositif sans qu'il soit nécessaire de procéder à un réarbitrage du bus hôte pour récupérer les données. Les données sont transmises sur le bus hôte lorsque celui-ci est inactif, même lorsque le bus hôte est commandé par un autre dispositif.