公开(公告)号：DE3942431C2

公开(公告)日：1991-09-26

申请号：DE3942431

申请日：1989-12-21

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, DAEJEON, KR ,  KOREA TELECOMMUNICATION AUTHORITY, SEOUL/SOUL, KR

Inventor： LEE, BHUM CHEOL, CHUNGNAM, KR ,  PARK, KWON CHUL, DAEJEON, KR

IPC: H03L7/00 ,  H04L7/00 ,  H04L7/027 ,  H04L7/033 ,  H04L25/40

Abstract: A frequency and phase detection circuit in an NRZ bit synchronous system by simultaneously retiming an NRZ input with an in-phase clock and an inverse-phase clock, respectively. A first frequency and phase difference is extracted by supplying the retimed NRZ with the in-phase clock and the delay-compensated NRZ input to an exclusive OR-gate. A second frequency and phase difference is extracted by supplying the retimed NRZ with the inverse-phase clock and the retimed NRZ with the in-phase clock to another exclusive OR-gate.

公开(公告)号：DE3941252A1

公开(公告)日：1990-06-21

申请号：DE3941252

申请日：1989-12-14

Applicant: ELECTRONIC & TELECOMM RES INST ,  KOREA TELECOMMUNICATION

Inventor： LEE BHUM CHEOL ,  PARK KWON CHUL ,  KIM BONG TAE

IPC: H04L7/00 ,  H04J3/06 ,  H04L7/08

Abstract: A reframe circuit in a synchronous multiplexing device comprising a frame synchronizing pattern detection circuit, a frame pattern bit error detection circuit responsive to a serial data stream from the frame synchronizing pattern detection circuit, an in-frame/out-of-frame state discrimination circuit responsive to the output signal from the frame pattern bit error detection circuit and the output signal from the synchronizing pattern detection circuit, a counter phase synchronizing circuit responsive to the output signal from the in-frame/out-of-frame state discrimination circuit, the output signal from the frame synchronization pattern detection circuit and a reference phase signal, and a counter and timing generation circuit responsive to the operating mode control signal from the counter phase synchronizing circuit.

公开(公告)号：GB2382741A

公开(公告)日：2003-06-04

申请号：GB0205436

申请日：2002-03-08

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： NAM HONG-SOON ,  HAN MAN-SOO ,  RHEE WOO-SEOP ,  YONG-ILJUN

IPC: H04L12/54 ,  H04L47/52 ,  H04L12/56

Abstract: Disclosed herein is an apparatus and method for scheduling packets using a credit based round robin in a high-speed communication network in which packets are transmitted to and received from a plurality of connections having respective speeds of service. The scheduling apparatus includes a packet pool 33 for storing input packets 31; a token queue 35 for storing tokens 36 each having a connection identifier (ID) of an input packet 31 stored in said packet pool 33, the round number (RN) of the connection, and a credit value (CV) for service; and a connection management unit 34 for transmitting the input packets 31 to said packet pool 33, reading the packets stored in said packet pool 33, generating the tokens 36 each having a connection identifier (ID) of an input packet 31 stored in said packet pool 33, the round number (RN) of the connection, and a credit value (CV) for service and transmitting them to said token queue 35, and servicing the packets of said packet pool designated by the token 36 stored in said token queue 35.

公开(公告)号：GB2347815A

公开(公告)日：2000-09-13

申请号：GB0013542

申请日：1997-05-27

Applicant: KOREA TELECOMMUNICATION

Inventor： KIM SUNG RYONG ,  KIM YOUNG MAN ,  BAIK SONG HOON ,  KIM HYO SIL ,  JEONG JAE WOO

IPC: G06K9/00

Abstract: A method for automatically verifying the accuracy of an electronic map is described. The method includes determining whether a symbol-affixed line is a symmetric line or an asymmetric line, thereby defining a figure which may receive a symbol. The number of symbols of the symbol-affixed line received in the defined figure during movement of the figure along the symbol-affixed line is calculated, and an ideal number of symbols is calculated. The method then verifies the accuracy of the electronic map, based on the calculated results along with desired limitations associated with those results.

公开(公告)号：GB2319127B

公开(公告)日：2000-09-06

申请号：GB9720799

申请日：1997-09-30

Applicant: KOREA TELECOMMUNICATION

Inventor： HAN IL SONG ,  CHOI YOUNG JAE ,  KIM DAE HWAN

IPC: G06F3/05 ,  H03K21/00 ,  H03M1/54 ,  H03M1/60

Abstract: Apparatus for converting a voltage into pulses has a charging part 11 receiving the voltage, a voltage comparing part 12 for comparing the output voltage from the charging part 11 with a reference voltage value, a pulse extracting part 13 for outputting pulses in response to the comparison result; and a discharging part 14 for discharging the charge in the charging part 11 in response to the output signal of the pulse extracting part 13 or the comparing part 12.

公开(公告)号：GB2317980B

公开(公告)日：2000-09-06

申请号：GB9720798

申请日：1997-09-30

Applicant: KOREA TELECOMMUNICATION

Inventor： HAN IL SONG

IPC: G06G7/14 ,  G06F7/44 ,  G06G7/164 ,  G06G7/60 ,  G06G7/163

Abstract: A multiplier capable of removing nonlinear current using current mirror circuits. The multiplier uses MOSFET and BJT devices by the BiCOMS processes. The multiplier includes three current mirror circuits. A first current mirror includes a BJT Q3 and a BJT Q5 and also the BJT Q3 is coupled in series to the n-channel MOSFET M1 between the voltage V1 and a ground voltage level. A second current mirror includes a BJT Q7 and a BJT Q8. A third current mirror includes a BJT Q4 and a BJT Q6. Consequently, input voltage signals V1 and Vdc applied to the n-channel MOSFETs M1 determine the current I1 and input voltage signals V1 and V2 applied to the n-channel MOSFET M2 determine the current I2.

公开(公告)号：FR2754119B1

公开(公告)日：1999-07-30

申请号：FR9712278

申请日：1997-10-02

Applicant: KOREA TELECOMMUNICATION

Inventor： HAN IL SONG

IPC: G06G7/28 ,  G06F15/18 ,  G06N3/06 ,  G06N3/063 ,  H03K4/00 ,  G06F15/80

Abstract: Control-type continuous ramp converting apparatus and method therefore. The present invention provides real-time processing of neurons in the neural network, easy implementation and reduction of manufacture cost of high density neurons in the neural network. The present invention comprises a first voltage controlling part for receiving a first voltage from an outside, and for non-linearly increasing a charged voltage in accordance with a differential continuous function of an exponential function; a second voltage controlling part for receiving a second voltage from an outside, and for non-linearly reducing a charged voltage in accordance with a differential continuous function of an exponential function; a charging part for charging an input current, and for providing the charged voltage of the charging part with the second voltage controlling part and an outside; and a plurality of switches for coupling outside and the first and the second voltage controlling part to the charging part, for selectively providing a third voltage from outside, an increased voltage and a decreased voltage based on the voltage of the charging part.

公开(公告)号：DE69324555D1

公开(公告)日：1999-05-27

申请号：DE69324555

申请日：1993-06-18

Applicant: KOREA TELECOMMUNICATION

Inventor： KIM EUN ,  JIN BYUNG ,  JOO WOON ,  YOON JEONG

IPC: H04M17/00 ,  H04M3/24 ,  H04M17/02

Abstract: A coin/credit operated public telephone is capable of making local, toll, and international calls using coins, credit card, or IC card and also of making a voice announcement regarding its operation method to the caller through a handset (1). Moreover, it provides graphic/character information through the LCD (10) and can transmit fault status that has been detected as a result of a highly reliable self-diagnosis carried out by receiving control signals from a remotely located central management system.

公开(公告)号：DE4222844C2

公开(公告)日：1999-05-27

申请号：DE4222844

申请日：1992-07-11

Applicant: KOREA TELECOMMUNICATION

IPC: G06G7/163 ,  G06N3/063 ,  H03F3/16

Abstract: A MOSFET analog multiplier with a variable resistive MOSFET linear means for linearly varying output current I depending upon a symmetrical input voltage from voltage sources V2 and -V2 and an input voltage from an input voltage source V1 operatively associated with the symmetrical input voltage from the voltage source V2 and -V2, with the variable resistive MOSFET linear means having a node A to output the varied output current I therethrough is disclosed. An operational amplifying unit for amplifying the linearly varied output current I and which includes an operational amplifier U with an inverting input terminal connected to the node A of the MOSFET linear means, a non-inverting input terminal connected to ground, and an output terminal. The operational amplifying unit further includes a feedback element Z connected between the inverting input terminal and the output terminal of the operational amplifier U, where in use the output terminal outputs a voltage Vo.

公开(公告)号：CA2115838C

公开(公告)日：1998-07-14

申请号：CA2115838

申请日：1993-06-18

Applicant: KOREA TELECOMMUNICATION

Inventor： KWON SOON H ,  KIM EUN H ,  JIN BYUNG W ,  JOO WOON Y

IPC: G07D3/00 ,  G07D3/04 ,  G07D13/00 ,  G07F5/24

Abstract: A coin treatment apparatus, for selecting the inserted coins by each currency un it, transferring them to a receiving space of a predetermined position, and discharging various coins stored in the receiving space into a coin receiving box (3) which is another receiving space, is constructed.