公开(公告)号：EP1879397A2

公开(公告)日：2008-01-16

申请号：EP07111480.5

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig c/o MicroUnity, Inc. ,  Moussouris, John c/o MicroUnity, Inc.

IPC: H04N7/24 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

公开(公告)号：EP1876524A2

公开(公告)日：2008-01-09

申请号：EP07111351.8

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig c/o MicroUnity, Inc. ,  Moussouris, John c/o MicroUnity, Inc.

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

Abstract translation: 一种用于处理和发送媒体数据流的通用可编程媒体处理器（12）。 媒体处理器（12）包括执行单元（100），其通过媒体数据流保持基本上峰值数据。 执行单元（100）包括动态分离多精度运算单元（102），可编程开关（104）和可编程扩展数学元件（106）。 高带宽外部接口（124）以基本上峰值的速率将媒体数据流提供给通用寄存器文件（110）和执行单元。 提供存储器管理单元，以及指令和数据高速缓冲存储器/缓冲器（118,120）。 通用的可编程媒体处理器（12）被布置在由光纤电缆，同轴电缆和双绞线组成的网络结构中，以传输，处理和接收单个或统一的媒体数据流。

公开(公告)号：EP1236090A1

公开(公告)日：2002-09-04

申请号：EP00910150.2

申请日：2000-02-11

Applicant: Microunity Systems Engineering, Inc.

Inventor： HANSEN, Craig ,  BATEMAN, Bruce ,  MOUSSOURIS, John

IPC: G06F9/30

CPC classification number: G06F7/76 ,  G06F9/30018

Abstract: The present invention provides a cross-bar circuit (100) that implements a switch (115) of a broadband processor. The cross-bar circuit (100) includes: a switch circuit (115) which includes 2m.2n:1 multiplexor circuits (202-204) where each of the 2n:1 multiplexor circuits (202-204) has a unique n-bit index input, one disable input, and a 2n-bit wide source input receives an n-bit index at the n-bit index input, a disable bit at the disable input, and the 2n-bit input source word at the 2n-bit wide source input, and decodes the n-bit index either to select and output as an output destination bit one bit from the 2n-bit input source word if the disable bit has a logic low value; a cache memory (110) that has 2m cache datapath inputs; and 2m cache index input; and a control circuit (105) that has a plurality of control inputs receives the partially decoded instruction information on the plurality of control inputs, provides a second set of the n-bit indexes for the switch circuit (115), and provides the disable bits for the switch circuit (115) where the control circuit (105) is logically coupled to the switch circuit (115) and to the cache memory (110).

公开(公告)号：EP0979448A1

公开(公告)日：2000-02-16

申请号：EP97935017.0

申请日：1997-07-21

Applicant: Microunity Systems Engineering, Inc.

Inventor： LAIDIG, Thomas, L.

IPC: G06F9/00 ,  G06F17/50

CPC classification number: G06F17/5081

Abstract: A system for processing geometry which reduces the amount of memory spaces while improving the processing speed. The system delivers vertices in sequence to a vertex queue (70) so that data in the vertex queue is freed as it is delivered and only minimal intermediate results are stored. By this incremental evaluation, less memory space is needed. In another aspect of the invention the vertices are maintained in the proper sequence so that sorting operation can be eliminated. A sorted vertex queue (70) and an unsorted vertex list (72) are utilized so that resorting of the entire vertex list may be prevented. In addition, a compressed format (34) for storing geometry is utilized based on the fact that much information can be rederived from a sorted and reduced vertex queue.

公开(公告)号：EP0628226A1

公开(公告)日：1994-12-14

申请号：EP93907156.0

申请日：1993-02-23

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： ROSSEEL, Geert ,  HERNDON, William, H. ,  MATTHEWS, James, A.

IPC: H03K19 ,  H03K17

CPC classification number: H03K19/086 ,  H03K17/14 ,  H03K17/567 ,  H03K17/603 ,  H03K19/09448

Abstract: Circuit logique BICMOS amélioré (70) utilisant une paire de transistors bipolaires (21, 22) à couplage par émetteurs pour comparer de manière différentielle un signal d'entrée (Vin) et un niveau de référence logique (VBIAS). Chaque transistor bipolaire est chargé de manière résistive par un réseau de transistors (26, 27) à semiconducteur à grille isolée par oxyde métallique à canal P (PMOS) couplés en parallèle. La grille d'au moins une des combinaisons parallèles de transistors est couplée à un signal de commande (VREF2) fournissant une résistance de charge variable. De préférence, le signal de commande est fourni par un réseau de retour (52, 53) servant à maintenir à une valeur constante l'excursion de tension constante dans le réseau, malgré les variations de température.

公开(公告)号：EP0609351A1

公开(公告)日：1994-08-10

申请号：EP92922539.0

申请日：1992-10-19

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： MATTHEWS, James, A.

IPC: H01L29 ,  H01L21

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/36 ,  H01L29/732 ,  Y10S148/01

Abstract: Transistor bipolaire possédant un émetteur (25), une base (31) et un collecteur (30). Il comprend une zone de base intrinsèque (33) à zones latérales étroites (p-) et à zone centrale plus large (37). Les zones latérales sont contiguës à la zone dopée (31), et la zone centrale (37) se trouve sous l'émetteur (25). Le profil de dopage latéral de la base est tel que les concentrations de dopage dans la zone dopée (31) et la zone centrale (37) sont relativement élevées par rapport à celles dans les zones latérales étroites (p-) de la base intrinsèque (33). L'association des zones latérales étroites (p-) au profil de dopage latéral de la base limite l'étendue de la zone de déplétion à l'intérieur de la base, ce qui assure une réduction de la tension de claquage du transistor sans entraîner une perte du gain en courant.

公开(公告)号：EP3161616A2

公开(公告)日：2017-05-03

申请号：EP15815691.9

申请日：2015-06-26

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： HANSEN, Craig ,  MOUSSOURIS, John ,  MASSALIN, Alexia

IPC: G06F9/30

CPC classification number: G06F12/0875 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/3895 ,  G06F2212/452

Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.

Abstract translation: 公开了可扩展的宽操作，其中在执行指令中使用比处理器和存储器之间的数据路径更宽的操作数。 可扩展的宽操作数减少了执行计算的功能单元的设计中相关处理器的特性的影响，包括寄存器文件的宽度，处理器时钟速率，处理器的异常子系统以及加载中的操作顺序 并在宽缓存中使用操作数。

公开(公告)号：EP1879398B1

公开(公告)日：2012-06-06

申请号：EP07112548.8

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig ,  Moussouris, John

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

公开(公告)号：EP1873630B8

公开(公告)日：2012-02-29

申请号：EP07111352.6

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig ,  Moussouris, John

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

公开(公告)号：EP2241968A2

公开(公告)日：2010-10-20

申请号：EP10160103.7

申请日：1999-08-24

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig

IPC: G06F9/30

CPC classification number: G06F9/30014 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3885 ,  G06F12/0886

Abstract: A general purpose processor with four copies of an access unit, with an access instruction fetch queue A-queue (101-104). Each A-queue (101-104) is coupled to an access register file AR (105-108) which is coupled to two access functional units A (109-116). In a typical embodiment, each thread of the processor may have on the order of sixty-four general purpose registers. The access unit functions independently by four simultaneous threads of execution, and each compute control flow by performing arithmetic and branch instructions and access memory by performing load and store instructions. These access units also provide wide specifiers for wide operand instructions. These eight access functional units A (109-116) produce results for access register files (105-108) and memory addresses to a shared memory system (117-120).

Abstract translation: 具有访问单元的四个副本的通用处理器，具有访问指令获取队列A队列（101-104）。 每个A队列（101-104）耦合到耦合到两个访问功能单元A（109-116）的访问寄存器文件AR（105-108）。 在典型的实施例中，处理器的每个线程可以具有六十四个通用寄存器的数量级。 访问单元通过四个同时执行的线程独立地起作用，并且通过执行加载和存储指令来执行算术和分支指令以及访问存储器来进行每个计算控制流程。 这些访问单元还提供广泛的操作数说明。 这八个访问功能单元A（109-116）产生访问寄存器文件（105-108）和存储器地址到共享存储器系统（117-120）的结果。