公开(公告)号：EP0389142B1

公开(公告)日：1995-07-12

申请号：EP90302343.0

申请日：1990-03-06

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Wise, Adrian Philip ,  Forsyth, Richard Matthew

IPC: G11C7/00 ,  G11C11/41 ,  G11C8/00

CPC classification number: G11C11/419 ,  G11C7/10 ,  G11C7/1018

公开(公告)号：EP0411818B1

公开(公告)日：1995-06-14

申请号：EP90308152.9

申请日：1990-07-25

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Ferris, Andrew Timothy ,  Work, Gordon Stirling

IPC: G11C11/419 ,  G11C7/06

CPC classification number: G11C11/419 ,  G11C7/065 ,  G11C2207/063

公开(公告)号：EP0523854B1

公开(公告)日：1995-05-31

申请号：EP92305478.7

申请日：1992-06-15

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Cytera, Christopher ,  Hall, Andrew Medlicott

IPC: H03L7/099 ,  H03B5/24

CPC classification number: H03L7/0995 ,  H03B5/24 ,  H03B27/00 ,  H03B2200/0038 ,  H03B2200/0058 ,  H03B2200/0062 ,  H03B2200/0078 ,  H03B2201/02 ,  H03L1/00

公开(公告)号：EP0646905A1

公开(公告)日：1995-04-05

申请号：EP94306901.3

申请日：1994-09-21

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Chowdhury, Vivek

IPC: G09G3/30

CPC classification number: G09G3/2011 ,  G09G3/30 ,  G09G2310/0275 ,  G09G2310/0289 ,  H04N3/14

Abstract: A driver circuit has an input stage (2) with an input node for receiving a control signal (DRIVE-IN). A capacitor circuit (4) is connected to the input node and a first power supply (VRAMP) and is arranged to be charged up by said first power supply (VRAMP) under the control of the control signal (DRIVE-IN). The driver circuit also has an output stage (6) connected to a second power supply (Vpp) and is arranged to provide a driver signal (POUT) in dependence on the charge stored at the capacitor circuit (4). A buffer circuit (8) is connected between the capacitor circuit (4) and the output stage (6).

Abstract translation: 驱动器电路具有输入级（2），其具有用于接收控制信号（DRIVE-IN）的输入节点。 电容器电路（4）连接到输入节点和第一电源（VRAMP），并且被布置成在控制信号（DRIVE-IN）的控制下被所述第一电源（VRAMP）充电。 驱动器电路还具有连接到第二电源（Vpp）的输出级（6），并且被配置为根据存储在电容器电路（4）的电荷来提供驱动器信号（POUT）。 缓冲电路（8）连接在电容电路（4）和输出级（6）之间。

公开(公告)号：EP0645891A1

公开(公告)日：1995-03-29

申请号：EP94306134.1

申请日：1994-08-19

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Horsfall, Wayne Leslie ,  Shipton, Gary

IPC: H03L7/113 ,  H03D3/24

CPC classification number: H03L7/113 ,  H03D3/244

Abstract: Apparatus for setting up the tuning frequency of a phase locked loop is provided which utilises the voltage controlled oscillator of the phase locked loop itself. The apparatus includes signal translation circuitry which can provide a control voltage to the VCO of the phase locked loop dependent on a tuning voltage which is alterable in response to the frequency of the signal output by the VCO.

Abstract translation: 提供了用于设置锁相环的调谐频率的装置，其利用锁相环本身的压控振荡器。 该装置包括信号转换电路，其可以根据可响应于VCO输出的信号的频率而改变的调谐电压向VCO的VCO提供控制电压。

公开(公告)号：EP0587399A3

公开(公告)日：1994-11-30

申请号：EP93307034.4

申请日：1993-09-07

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Nicholls, Howard Charles ,  Norrington, Michael John

IPC: H01L23/48 ,  H01L21/283

CPC classification number: H01L21/76877 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S257/90 ,  H01L2924/00

Abstract: A semiconductor device comprising a silicon substrate (2,10), an oxide layer (4) on the silicon substrate, a doped polysilicon region (6) disposed on the oxide layer, a dielectric layer (14) which has been deposited over the doped polysilicon region (6) and the silicon substrate, a contact hole (16) which is formed in the dielectric layer (14) and extends over respective laterally adjacent portions of the doped polysilicon region (6) and the silicon substrate (2,10) and a contact (20) which has been selectively deposited in the contact hole which electrically connects the said portions together. The invention also provides a method of fabricating a semiconductor device incorporating a refractory metal contact, the method comprising the steps of:- a) providing a semiconductor substrate (2,10) having an oxide layer (4) thereon and a doped polysilicon region (6) disposed on the oxide layer; (b) depositing a dielectric layer (14) over the doped polysilicon region and over the silicon substrate; (c) forming a contact hole (16) in the dielectric layer which exposes a portion of the doped polysilicon region and a laterally adjacent portion of the silicon substrate; and (d) selectively depositing a contact (20) into the contact hole thereby electrically to connect together the doped polysilicon region and the silicon substrate.

Abstract translation: 一种半导体器件，包括硅衬底，硅衬底上的氧化物层，设置在氧化物层上的掺杂多晶硅区域，沉积在掺杂多晶硅区域和硅衬底上的电介质层，形成在 电介质层并且延伸在掺杂多晶硅区域和硅衬底的相应的横向相邻部分上，以及已经选择性地沉积在将所述部分电连接在一起的接触孔中的触点。 本发明还提供了一种制造包含难熔金属接触的半导体器件的方法，该方法包括以下步骤：a）提供其上具有氧化物层的半导体衬底和设置在氧化物层上的掺杂多晶硅区域; （b）在所述掺杂多晶硅区域上并在所述硅衬底上沉积介电层; （c）在所述电介质层中形成暴露所述掺杂多晶硅区域的一部分和所述硅衬底的横向相邻部分的接触孔; 和（d）选择性地将触点沉积到所述接触孔中，从而电连接所述掺杂多晶硅区域和所述硅衬底。

公开(公告)号：EP0422939A2

公开(公告)日：1991-04-17

申请号：EP90311168.0

申请日：1990-10-11

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Ferris, Andrew Timothy ,  Work, Gordon Stirling

IPC: G11C7/00

CPC classification number: G11C7/22 ,  G11C7/14 ,  Y10S438/926

Abstract: A memory circuit comprises a plurality of memory cells (2) arranged in rows and columns, the cells in each row being connected to a common word line (4) and the cells in each column being connected between a pair of bit lines (6,8) across which a voltage differential is developed when a memory cell is accessed to be read; and a timing circuit (16) for producing a timing signal to control further circuitry in dependence on said voltage differential achieving a predetermined value. The memory circuit has a dummy bit line connected to a column of dummy cells, each dummy cell having the same structure as a memory cell. A plurality of said dummy cells (22) has a bit value stored therein and is connected to a dummy word line and the remainder of said dummy cells are rendered inactive, whereby on addressing of the dummy wordline simultaneously with the wordline of an accessed cell, a predetermined number of dummy cells discharges via the dummy bit line so that the voltage developed on the dummy bit line is a fixed multiple of the voltage differential developed between the bit lines of the accessed cell. The timing circuit (16) is connected to receive the voltage differential on the dummy bit line (18).

Abstract translation: 存储器电路包括以行和列排列的多个存储器单元（2），每行中的单元连接到公共字线（4），并且每列中的单元连接在一对位线（6， 8），当访问存储器单元以读取时，产生电压差; 以及定时电路（16），用于产生定时信号，以根据实现预定值的所述电压差来控制另外的电路。 存储电路具有连接到虚拟单元列的虚拟位线，每个虚设单元具有与存储单元相同的结构。 多个所述虚拟单元（22）具有存储在其中的位值，并且连接到虚拟字线，并且所述虚拟单元的剩余部分变为非活动状态，由此在与被访问单元格的字线同时寻址伪字线的情况下， 预定数量的虚拟单元经由虚拟位线放电，使得在虚拟位线上产生的电压是在所访问的单元的位线之间产生的电压差的固定倍数。 定时电路（16）被连接以接收虚拟位线（18）上的电压差。

公开(公告)号：EP0391562A3

公开(公告)日：1991-03-13

申请号：EP90302869.4

申请日：1990-03-16

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Nicholls, Howard Charles ,  Norrington, Michael John ,  Thompson, Michael Kevin

IPC: H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76877 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a tungsten contact in a semiconductor device, which method comprises the steps of:-
(a) providing an oxide layer (34) on a region of a silicon substrate; (b) depositing a sealing dielectric layer (44) over the oxide layer; (c) depositing an interlevel dielectric layer (46) over the sealing layer; (d) etching through the interlevel dielectric layer, the sealing dielectric layer and the oxide layer as far as the substrate thereby to form a contact hole and to expose the said region; (e) implanting a dopant into the said region whereby the implanted dopant is self-aligned to the contact hole; (f) thermally annealing the substrate; (g) selectively depositing tungsten in the contact hole; and (h) depositing an interconnect layer over the deposited tungsten contact. The invention also provides a semiconductor device.

公开(公告)号：EP0411818A2

公开(公告)日：1991-02-06

申请号：EP90308152.9

申请日：1990-07-25

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Ferris, Andrew Timothy ,  Work, Gordon Stirling

IPC: G11C11/419 ,  G11C7/06

CPC classification number: G11C11/419 ,  G11C7/065 ,  G11C2207/063

Abstract: A current sensing amplifier has two crosscoupled input p-channel transistors, two load transistors connected respectively to the input transistors and a switch element. Output voltages are developed across the load transistors. The amplifier senses differences in currents supplied to the input transistors and drives the output voltages in opposite directions in a sense dependent on the sense of the difference of the currents.

Abstract translation: 电流感测放大器具有两个交叉耦合的输入p沟道晶体管，两个负载晶体管分别连接到输入晶体管和开关元件。 跨负载晶体管产生输出电压。 放大器感测提供给输入晶体管的电流差异，并在某种意义上驱动输出电压在相反方向，这取决于电流差异的感觉。

公开(公告)号：EP0409434A1

公开(公告)日：1991-01-23

申请号：EP90307109.0

申请日：1990-06-28

Applicant: SGS-Thomson Microelectronics Limited

Inventor： May, Michael David ,  Parsons, Brian Jeremy ,  Thompson, Peter William ,  Walker, Christopher Paul Hulme

IPC: G06F15/16

CPC classification number: G06F15/17343 ,  G06F15/17 ,  H04L29/00

Abstract: A computer device comprises a processor (2) for executing a plurality of concurrent processes each comprising a sequence of instructions, memory (4) including RAM, at least one message link (10) having input and output pins (12) for connection to a device separate from said computer device and for transmitting message packets sequentially between the computer device and said separate device, and communication control circuitry (6) coupled to said processor, to said memory, and to said message link. The memory provides a plurality of addressable virtual communication links. The communication control circuitry is operable:

(i) in response to execution of a message instruction by said processor to address a selected one of said virtual communication links and load into the selected one information regarding the message to be effected via the virtual communication link; and
(ii) to control sequential transmission through said one message link of message packets relating to a plurality of virtual communication links.

A network of such computer devices and a method of operation is also described. The provision of virtual links enables several messages to be multiplexed down a single message link of the microcomputer.

Abstract translation: 计算机设备包括：处理器（2），用于执行多个并发处理，每个处理器包括一系列指令;存储器（4），包括RAM;至少一个消息链路（10），具有输入和输出引脚（12） 设备与所述计算机设备分开并用于在计算机设备和所述单独设备之间顺序发送消息分组，以及连接到所述处理器的通信控制电路（6），所述存储器以及所述消息链路。 存储器提供多个可寻址的虚拟通信链路。 通信控制电路可操作：（i）响应于所述处理器执行消息指令以寻址所选择的所述虚拟通信链路中的一个，并将所述一个关于要通过所述虚拟通信链路进行的消息的信息加载到所选择的一个信息中; 以及（ii）控制通过与多个虚拟通信链路有关的消息分组的所述一个消息链路的顺序传输。 还描述了这种计算机设备的网络和操作方法。 虚拟链路的提供使得几个消息可以在微计算机的单个消息链路下复用。