公开(公告)号：KR101027787B1

公开(公告)日：2011-04-07

申请号：KR1020090135602

申请日：2009-12-31

Applicant: 고려대학교 산학협력단

Inventor： 김태근 ,  안호명 ,  김희동

IPC: H01L27/115 ,  H01L21/8247 ,  G11C16/02

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  G11C16/02 ,  H01L29/517

Abstract: PURPOSE: A nonvolatile memory device for a multi level program is provided to execute the multi level program without using a resistance change material by forming a plurality of channel areas which conduct carriers with different application voltages. CONSTITUTION: A bottom electrode(110) is formed on a semiconductor substrate(100). An insulation layer(120) is formed on the bottom electrode. A top electrode(130) is formed on the insulation layer. A first channel area(121) is separated from the bottom electrode with a first gap. A second channel area(122) is separated from the bottom electrode with a second gap which is larger than the first gap.

Abstract translation: 目的：提供一种用于多电平程序的非易失性存储器件，用于通过形成具有不同施加电压的载流子的多个沟道区而不使用电阻变化材料来执行多电平程序。 构成：在半导体衬底（100）上形成底部电极（110）。 绝缘层（120）形成在底部电极上。 顶部电极（130）形成在绝缘层上。 第一通道区域（121）与第一间隙与底部电极分离。 第二通道区域（122）与底部电极分离，第二间隙大于第一间隙。

公开(公告)号：KR101011670B1

公开(公告)日：2011-01-28

申请号：KR1020090116586

申请日：2009-11-30

Applicant: 고려대학교 산학협력단

Inventor： 김태근 ,  안호명

IPC: G11C16/34 ,  G11C16/12 ,  G11C16/30

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/30 ,  G11C16/3418

Abstract: PURPOSE: A method for programming a nonvolatile memory device is provided to perform a multi bit program by locally injecting charges into a charge trapping layer adjacent to a drain region and a source region. CONSTITUTION: A semiconductor layer(400) including a charge trapping layer(420) is formed on a substrate. A source region(200) and a drain region are formed on both sides of the semiconductor layer. A reverse bias voltage over a breakdown voltage between the selection region and the substrate is applied between the substrate and one of a drain region or source region. A program is performed by inputting the charge of a high temperature which is generated from a junction between the selection region and the substrate to the charge trapping layer.

Abstract translation: 目的：提供一种用于编程非易失性存储器件的方法，用于通过将电荷局部注入到与漏极区域和源极区域相邻的电荷俘获层中来执行多位程序。 构成：在基板上形成包括电荷俘获层（420）的半导体层（400）。 源区域（200）和漏极区域形成在半导体层的两侧。 在衬底与漏极区域或源极区域之一之间施加在选择区域和衬底之间的击穿电压以上的反向偏置电压。 通过将从选择区域和基板之间的接合处产生的高温的电荷输入到电荷捕获层来执行程序。

公开(公告)号：KR1020090124478A

公开(公告)日：2009-12-03

申请号：KR1020080050723

申请日：2008-05-30

Applicant: 고려대학교 산학협력단

Inventor： 김태근 ,  김은홍 ,  종위안

IPC: H01L33/38

Abstract: PURPOSE: A light emitting diode in which electrode with mesh structure is formed and method for manufacturing the same is provided to control the size of the pattern of the columnar and to control the interval of the mesh structure and the width of the electrodes. CONSTITUTION: The semiconductor layer(500) generates the light. The electrode layer(700) is formed in the semiconductor layer into the mesh structure. The electrode layer is separated and is composed of a plurality of first electrode arrays(710) and parallelly formed a plurality of second electrode arrays(720). A plurality of second electrode is parallelly formed. First electrode and second electrode are formed in order to each other meet at right angle. The electrode layer is made of one among the Ni, Pt, Pd, Rh and Ag.

Abstract translation: 目的：提供一种其中形成有网状结构的电极的发光二极管及其制造方法，以控制柱状图案的尺寸并控制网格结构的间隔和电极的宽度。 构成：半导体层（500）产生光。 电极层（700）在半导体层中形成为网格结构。 电极层被分离并且由多个第一电极阵列（710）组成并平行地形成多个第二电极阵列（720）。 多个第二电极平行地形成。 第一电极和第二电极彼此成直角地形成。 电极层由Ni，Pt，Pd，Rh和Ag之一构成。

公开(公告)号：KR1020090120532A

公开(公告)日：2009-11-25

申请号：KR1020080046383

申请日：2008-05-20

Applicant: 고려대학교 산학협력단

Inventor： 김태근 ,  이완호

IPC: H01L33/10 ,  H01L33/20

CPC classification number: H01L33/405 ,  H01L33/42

Abstract: PURPOSE: A light emitting element with a bent reflecting layer and a manufacturing method thereof are provided to form a reflecting layer with high heat conductivity on the outside of a transparent electrode layer, thereby improving heat discharging efficiency. CONSTITUTION: A light emitting element with a bent reflecting layer and a manufacturing method thereof comprise the following steps. A light emitting layer generates light on a substrate. A transparent electrode layer(360) forms a bending on an upper surface of the light emitting layer. A reflecting layer(370) full-reflects the bending on the transparent electrode layer. The transparent electrode layer is formed on the light emitting layer. A photo resist is formed on the transparent electrode layer. The photo resist is removed to form a bending after wet etching.

Abstract translation: 目的：提供具有弯曲反射层的发光元件及其制造方法，以在透明电极层的外侧形成具有高导热性的反射层，从而提高放热效率。 构成：具有弯曲反射层的发光元件及其制造方法包括以下步骤。 发光层在基板上产生光。 透明电极层（360）在发光层的上表面上形成弯曲。 反射层（370）全反射透明电极层上的弯曲。 透明电极层形成在发光层上。 在透明电极层上形成光刻胶。 在湿蚀刻之后，去除光致抗蚀剂以形成弯曲。

公开(公告)号：KR1020090116278A

公开(公告)日：2009-11-11

申请号：KR1020080042128

申请日：2008-05-07

Applicant: 고려대학교 산학협력단

Inventor： 김태근 ,  안호명

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/06 ,  G11C16/10 ,  H01L21/28273 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144

Abstract: PURPOSE: A nonvolatile memory device and a manufacturing method thereof are provided to minimize a volume of a memory cell and increase an operation speed by combining a flash memory with an SONOS structure and a phase change nonvolatile memory. CONSTITUTION: An insulation layer(510) is formed on a substrate(500) and prevents the charge trapped in a charge trapping layer(520) from being induced to the substrate. The charge trapping layer is formed in the insulation layer and traps the charge. A plurality of phase change layers(532-1,532-2,532-3) control the flow and outflow of the charge between the charge trapping layer and a gate electrode layer(540). The gate electrode layer changes the state of the phase change layer according to the intensity of the current or voltage and the application time from the outside. The state of the phase change layer is the crystalline state or amorphous state. The gate electrode layer is made of aluminum or aluminum alloy.

Abstract translation: 目的：提供一种非易失性存储器件及其制造方法，以通过组合闪存与SONOS结构和相变非易失性存储器来最小化存储单元的体积并提高操作速度。 构成：在衬底（500）上形成绝缘层（510），并且防止俘获在电荷俘获层（520）中的电荷被引入衬底。 电荷捕获层形成在绝缘层中并捕获电荷。 多个相变层（532-1,532-2,532-3）控制电荷捕获层和栅极电极层（540）之间的电荷的流动和流出。 栅极电极层根据电流或电压的强度以及来自外部的施加时间来改变相变层的状态。 相变层的状态是晶态或非晶状态。 栅电极层由铝或铝合金制成。

公开(公告)号：KR1020090081693A

公开(公告)日：2009-07-29

申请号：KR1020080007690

申请日：2008-01-24

Applicant: 고려대학교 산학협력단

Inventor： 김태근 ,  김은홍 ,  김동호

IPC: H01L33/12

Abstract: A nitride semiconductor and a manufacturing method thereof are provided to discharge the heat generated in the device by using metal based material with high thermal conductivity. A buffer layer(212) is formed in order to be lattice-matched with a nitride epitaxial layer on a substrate. The nitride epitaxial layer(300) is formed on the buffer layer. A surface of the buffer layer is processed by using a predetermined etching process. The nitride epitaxial layer is formed in the buffer layer whose surface is processed.

Abstract translation: 提供氮化物半导体及其制造方法，以通过使用具有高导热性的金属基材料来排出器件中产生的热量。 形成缓冲层（212）以便与衬底上的氮化物外延层晶格匹配。 氮化物外延层（300）形成在缓冲层上。 通过使用预定的蚀刻工艺处理缓冲层的表面。 氮化物外延层形成在其表面被处理的缓冲层中。

公开(公告)号：KR100890212B1

公开(公告)日：2009-03-25

申请号：KR1020070120156

申请日：2007-11-23

Applicant: 고려대학교 산학협력단

Inventor： 김태근 ,  안호명 ,  김경찬

IPC: H01L27/115

CPC classification number: H01L45/06 ,  H01L21/28273 ,  H01L29/517 ,  H01L45/1233 ,  H01L45/144

Abstract: A non-volatile memory device and a manufacturing method thereof are provided to improve the working speed while minimizing the volume of the memory cell by uniting the flash memory and the phase change non-volatile memory. An insulating layer(510) is formed on the substrate(500) and blocks that the electric charges captured up in the charge trapping layer(520) is flowed out into the substrate. A phase-change layer(530) is formed with the phase change material on the charge trapping layer. The phase-change layer is changed to the crystalline state or the amorphous state by the heat applied to the gate electrode layer. The phase-change layer in the crystalline state allows the flow of the electric charge between the charge trapping layer and the gate electrode layer. The phase-change layer in the amorphous state blocks the flow of the electric charge between the charge trapping layer and the gate electrode layer.

Abstract translation: 提供了一种非易失性存储器件及其制造方法，以通过将闪存和相变非易失性存储器结合在一起来最小化存储器单元的体积来提高工作速度。 绝缘层（510）形成在基板（500）上，并阻止在电荷捕获层（520）中捕获的电荷流出到基板中。 在电荷捕获层上形成有相变材料的相变层（530）。 通过施加到栅极电极层的热量将相变层改变为结晶状态或非晶态。 结晶状态的相变层允许电荷捕获层和栅极电极层之间的电荷流动。 非晶态的相变层阻挡电荷俘获层和栅极电极层之间的电荷的流动。

公开(公告)号：KR100890210B1

公开(公告)日：2009-03-25

申请号：KR1020070086921

申请日：2007-08-29

Applicant: 고려대학교 산학협력단

Inventor： 김태근 ,  안호명 ,  김경찬 ,  서유정 ,  김희동

IPC: H01L27/115

Abstract: 본 발명은 비휘발성 메모리 소자 및 그 제조 방법을 개시한다. 본 발명의 비휘발성 메모리 소자는, 하나의 메모리 셀내에서 멀티 레벨 프로그래밍을 구현하기 위해서, 각 레벨에서 전하를 축적하는 전하 포획층을 서로 단차지도록 형성함으로써, 멀티 레벨의 동작을 구현함에 있어서 용이하게 각 레벨의 문턱 전압의 분포를 분리하여 멀티 레벨 동작을 구현할 수 있는 효과가 있다. 또한, 본 발명은 각 레벨에서 전하를 축적하는 전하 포획층을 서로 단차지도록 형성함으로써, 단채널 효과를 억제하면서도 그 제조 공정이 종래의 멀티 레벨을 구현하는 비휘발성 메모리 소자 제조 공정보다 단순하여 제조 효율을 향상시키는 효과가 있다.

公开(公告)号：KR1020090021974A

公开(公告)日：2009-03-04

申请号：KR1020070086921

申请日：2007-08-29

Applicant: 고려대학교 산학협력단

Inventor： 김태근 ,  안호명 ,  김경찬 ,  서유정 ,  김희동

IPC: H01L27/115

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833

Abstract: A non-volatile memory device and a manufacturing method thereof are provided to suppress a short channel effect and to improve producing efficiency by forming a charge trap layer in a step type. A source region(552) and a drain region(554) are formed on a semiconductor substrate(500). A channel region is positioned between the source region and the drain region. A memory layer in which a tunnel insulating layer(510), a charge trap layer(520) and a blocking insulating layer(530) are successively formed is formed in the upper part of the channel region. A gate electrode layer(540) is formed in the upper part of the blocking insulating layer. The insulating layer spacer is formed around the memory device. The tunnel insulating layer is formed to be stepped and the charge trap layer formed in the tunnel insulating layer is stepped.

Abstract translation: 提供一种非易失性存储器件及其制造方法，以抑制短沟道效应，并且通过形成阶梯型的电荷陷阱层来提高生产效率。 在半导体衬底（500）上形成源区（552）和漏区（554）。 沟道区域位于源极区域和漏极区域之间。 在通道区域的上部形成有连续形成隧道绝缘层（510），电荷陷阱层（520）和阻挡绝缘层（530）的存储层。 栅极电极层（540）形成在阻挡绝缘层的上部。 绝缘层间隔件围绕存储器件形成。 隧道绝缘层形成为阶梯状，并且形成在隧道绝缘层中的电荷陷阱层是阶梯状的。

公开(公告)号：KR100868031B1

公开(公告)日：2008-11-11

申请号：KR1020070076056

申请日：2007-07-27

Applicant: 고려대학교 산학협력단

Inventor： 김태근 ,  안호명 ,  김경찬 ,  서유정 ,  김희동

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/42324 ,  G11C16/3404 ,  H01L21/265 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/517 ,  H01L29/788 ,  H01L29/792

Abstract: The non-volatile memory device of the low voltage, micro type, highly integrated, high reliability the manufacturing process and a method of manufacture thereof are provided without complicated and additional processes. The non-volatile memory device comprises as follows. The memory layer is formed in which the turner insulating layer(510), first charge trapping layer(520), electric charge isolation layer(530), second charge trapping layer(540), blocking insulation film(550) are successively formed on a semiconductor substrate. The gate electrode layer(560) is formed on the blocking insulation film. The first-level is shown in the state that the electric charge is not injected in the first charge trapping layer and the second charge injecting layer. The second level is shown in case the electric charge is injected in the first charge trapping layer. The third level is shown in case the electric charge is injected in the second charge trapping layer. The fourth level is shown in case the electric charge is altogether injected in the first charge trapping layer and the second charge trapping layer. The electric charge is injected through the blocking insulation film from the gate electrode layer to the second charge trapping layer in order to show the third level.

Abstract translation: 提供低电压，微型，高度集成，高可靠性的制造工艺及其制造方法的非易失性存储器件，而不需要复杂和额外的工艺。 非易失性存储器件包括如下。 形成存储层，其中在第一电荷俘获层（510），第一电荷俘获层（520），电荷隔离层（530），第二电荷俘获层（540），阻挡绝缘膜（550） 半导体衬底。 栅极电极层（560）形成在阻挡绝缘膜上。 在第一电荷俘获层和第二电荷注入层中不注入电荷的状态下示出第一级。 在电荷注入第一电荷俘获层的情况下示出第二电平。 在第二电荷俘获层中注入电荷的情况下示出第三电平。 在第一电荷捕获层和第二电荷俘获层中电荷总共注入的情况下示出第四电平。 为了显示第三级，电荷通过阻挡绝缘膜从栅极电极层注入到第二电荷俘获层。