公开(公告)号：KR1020100038986A

公开(公告)日：2010-04-15

申请号：KR1020080098170

申请日：2008-10-07

Applicant: 삼성전자주식회사 ,  성균관대학교산학협력단

Inventor： 송이헌 ,  박재철 ,  권기원 ,  김선일

IPC: H01L27/10 ,  G02F1/13 ,  G02F1/136

CPC classification number: G11C13/00 ,  G11C5/02 ,  G11C13/0023 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/0688 ,  H01L27/1021 ,  H01L27/1052 ,  H01L27/1225 ,  H01L29/7869

Abstract: PURPOSE: A stack memory device including an oxide thin film transistor is provided to improve integration by minimizing an area of an active circuit unit even through the stacked memory layer increases. CONSTITUTION: A stack memory device includes an active circuit unit(10), a row line(12), and a column line(14). The low line and the column line are electrically connected to the active circuit. A selection transistor is formed on the same plane on the one end of the row line and column line of the memory array.

Abstract translation: 目的：提供包括氧化物薄膜晶体管的堆叠存储器件，以便即使通过堆叠的存储层增加，也可以通过使有源电路单元的面积最小化来提高积分。 构成：堆叠存储器件包括有源电路单元（10），行线（12）和列线（14）。 低线和列线电连接到有源电路。 选择晶体管形成在存储器阵列的行线和列线的一端的同一平面上。

公开(公告)号：KR1020100037407A

公开(公告)日：2010-04-09

申请号：KR1020080096721

申请日：2008-10-01

Applicant: 삼성전자주식회사

Inventor： 김상욱 ,  송이헌 ,  김창정 ,  박재철 ,  김선일

IPC: H01L21/336

CPC classification number: H01L27/0883 ,  H01L27/1203

Abstract: PURPOSE: An inverter, a method for operating the same, and a logic circuit including the same are provided to obtain a transistor which can easily control a threshold voltage by forming a load transistor or a driving transistor with a double gate structure. CONSTITUTION: A driving transistor(T2) is connected to a load transistor(T1). Either the driving transistor or the load transistor has a double gate structure. The load transistor is a depletion mode transistor or a depletion mode transistor with a double gate structure. The driving transistor is an enhancement mode transistor or the enhancement mode transistor with a double gate structure. The channel layer of the load transistor and the driving transistor includes a ZnO-based oxide.

Abstract translation: 目的：提供一种反相器，其操作方法和包括该反相器的逻辑电路，以获得能够通过形成具有双栅结构的负载晶体管或驱动晶体管来容易地控制阈值电压的晶体管。 构成：驱动晶体管（T2）连接到负载晶体管（T1）。 驱动晶体管或负载晶体管都具有双栅极结构。 负载晶体管是耗尽型晶体管或具有双栅结构的耗尽型晶体管。 驱动晶体管是增强型晶体管或具有双栅极结构的增强型晶体管。 负载晶体管的沟道层和驱动晶体管包括ZnO基氧化物。

公开(公告)号：KR1020100013717A

公开(公告)日：2010-02-10

申请号：KR1020080075349

申请日：2008-07-31

Applicant: 삼성전자주식회사

Inventor： 김창정 ,  김상욱 ,  김선일

IPC: H01L29/786 ,  H01L21/18

CPC classification number: H01L29/7869 ,  H01L29/26 ,  H01L29/06

Abstract: PURPOSE: An oxide semiconductor and a thin film transistor comprising the same are provided to reduce the change of a threshold voltage and improve mobility by adding a Hf for channel material into an oxide semiconductor. CONSTITUTION: In an oxide semiconductor, a channel(15) is installed to be corresponded to a gate(13). The channel includes an oxide semiconductor with added Hf into Ga-In-Zn oxide. A gate insulator(14) is formed between the gate and channel. Source and drains(16a,16b) are formed at the both side respectively touching with the channel. In the thin film transistor, the oxide is amorphous, or mixed crystalline, or a crystalline.

Abstract translation: 目的：提供一种氧化物半导体和包括该氧化物半导体的薄膜晶体管，以通过将氧化物半导体中的沟道材料添加Hf来减小阈值电压的变化并提高迁移率。 构成：在氧化物半导体中，通道（15）安装成对应于门（13）。 该沟道包括在Ga-In-Zn氧化物中添加了Hf的氧化物半导体。 栅极绝缘体（14）形成在栅极和沟道之间。 源极和漏极（16a，16b）形成在分别与沟道接触的两侧。 在薄膜晶体管中，氧化物是无定形的，或是混晶的，或是结晶的。

公开(公告)号：KR1020090014031A

公开(公告)日：2009-02-06

申请号：KR1020070078251

申请日：2007-08-03

Applicant: 삼성전자주식회사

Inventor： 전성찬 ,  김선일 ,  백찬욱 ,  김현진

IPC: H01P7/08

CPC classification number: H01P7/08 ,  H01P1/20345 ,  H01P1/20363

Abstract: A nano resonator tuning a frequency by using DC power is provided to control a vibration frequency of a resonator according to the variation of the DC voltage. A beam with a sandwich structure is fixed on a silicon wafer(200). The beam with the sandwich structure generates the mechanical vibration according to the alternating current and the applied magnetic field. The AC power source(220) applies the AC voltage in both ends of the beam with the sandwich structure. The DC power source(230) applies the DC voltage in both ends of the beam with the sandwich structure. The beam with the sandwich structure includes a silicon carbide beam(211), a first metallic conductor(212) and a second metallic conductor(214). The first metallic conductor is deposited on the silicon carbide beam. Both ends of the first metallic conductor are connected to the AC power source. The second metallic conductor is deposited on the first metallic conductor. Both ends of the second metallic conductor are connected to the DC power source.

Abstract translation: 提供通过使用DC电力调谐频率的纳米谐振器，以根据DC电压的变化来控制谐振器的振动频率。 具有夹层结构的梁固定在硅晶片（200）上。 具有夹层结构的梁根据交流电和施加的磁场产生机械振动。 交流电源（220）将三角形结构的梁的两端的交流电压施加。 直流电源（230）将两端的直流电压施加到夹层结构上。 具有夹层结构的梁包括碳化硅梁（211），第一金属导体（212）和第二金属导体（214）。 第一金属导体沉积在碳化硅束上。 第一金属导体的两端连接到AC电源。 第二金属导体沉积在第一金属导体上。 第二金属导体的两端连接到直流电源。

公开(公告)号：KR1020080111736A

公开(公告)日：2008-12-24

申请号：KR1020070060053

申请日：2007-06-19

Applicant: 삼성전자주식회사

Inventor： 김창정 ,  송이헌 ,  박영수 ,  이은하 ,  김선일

IPC: G02F1/136 ,  H01L29/786

CPC classification number: H01L29/22 ,  H01L21/02554 ,  H01L29/26 ,  H01L29/7869

Abstract: An oxide semiconductor and a thin film transistor having the same are provided to prevent hysteresis of the oxide thin film transistor, and improve the movement and on/off current characteristic. A gate(13) is formed on a substrate(11). A gate isolation layer(14) is formed on a substrate, and the gate. An oxide layer(12) is formed on the substrate if the substrate is Si substrate by the thermal oxidation process. A channel(15) is formed on the gate isolation layer corresponding to the gate. A source(16a) and a drain(16b) are formed on two part and gate isolation layer of channel.

Abstract translation: 设置氧化物半导体和具有该氧化物半导体的薄膜晶体管，以防止氧化物薄膜晶体管的滞后，并提高其移动和导通/截止电流特性。 在基板（11）上形成栅极（13）。 栅极隔离层（14）形成在衬底和栅极上。 如果衬底是通过热氧化工艺的Si衬底，则在衬底上形成氧化物层（12）。 在对应于栅极的栅极隔离层上形成沟道（15）。 源极（16a）和漏极（16b）形成在沟道的两部分和栅极隔离层上。

公开(公告)号：KR1020080105731A

公开(公告)日：2008-12-04

申请号：KR1020070053705

申请日：2007-06-01

Applicant: 삼성전자주식회사

Inventor： 전성찬 ,  김선일 ,  백찬욱

IPC: H01P7/00

CPC classification number: H03H9/2463 ,  B82Y15/00 ,  H03H9/02244 ,  Y10S977/712 ,  Y10S977/72 ,  Y10S977/724 ,  Y10S977/932

Abstract: A nano-resonator using beam with composite structure is provided to supply sufficient resonance at quasi-resonant condition without a magnetic line induced from super-conduction. In a nano-resonator using beam with composite structure, a support layer(213), having a sandwich structure while having low density, is deposited on the silicon carbide resonator(211). A sacrificial layer(212) is used for the bond of two layers having capable of enduring the high frequency resonance, and a support layer(213) is composed of mental having low density. A beam of the composite structure includes the silicon carbide beam, the metallic conductor of the low density evaporated on the sacrificial layer and the sacrificial layer evaporated on the silicon carbide beam.

Abstract translation: 使用具有复合结构的光束的纳米谐振器被提供以在准谐振条件下提供足够的谐振，而没有由超导导致的磁线。 在使用具有复合结构的光束的纳米谐振器中，在碳化硅谐振器（211）上沉积具有夹层结构而具有低密度的支撑层（213）。 牺牲层（212）用于能够承受高频共振的两层的结合，并且支撑层（213）由具有低密度的精神构成。 复合结构的梁包括碳化硅束，在牺牲层上蒸发的低密度的金属导体和在碳化硅束上蒸发的牺牲层。

公开(公告)号：KR100818281B1

公开(公告)日：2008-04-01

申请号：KR1020060104693

申请日：2006-10-26

Applicant: 삼성전자주식회사

Inventor： 최재영 ,  장지환 ,  김선일

IPC: G02B3/14 ,  G02B3/12

CPC classification number: G02B3/14 ,  G02B26/005

Abstract: An electrowetting lens is provided to form a cubic image regardless of the position of an observer by controlling the optical axis according to the position of the observer. In an electrowetting lens(30) having a substrate(31), a dielectric barrier(34) is set up on the substrate and formed in the shape of a cylinder or a polygonal cylinder having surfaces(34a,34b,34a',34b') facing each other. A hydrophobic coating layer is formed on the inner wall of the dielectric barrier. Polar and non-polar solutions(38,39) are filled in the dielectric barrier. First and second lower electrodes(32,33) contact with the polar solution through the lower part of the dielectric barrier. The first and second lower electrodes face each other. A split electrode is disposed in the surface of the dielectric barrier. The split electrode comprises first and second split electrodes(36,37) arranged in the surfaces of the dielectric barrier facing each other. The first and second split electrodes are split into plural electrode cells(361-36n,371-37n) according to the height direction of the dielectric barrier.

Abstract translation: 提供电润湿透镜，以通过根据观察者的位置控制光轴而与观察者的位置无关地形成立方体图像。 在具有基板（31）的电润湿透镜（30）中，在基板上设置电介质阻挡层（34），形成为具有表面（34a，34b，34a'，34b'）的圆柱体或多边形圆筒的形状， ）面对面。 在电介质屏障的内壁上形成疏水涂层。 极性和非极性溶液（38,39）填充在介质屏障中。 第一和第二下部电极（32,33）通过介电阻挡层的下部与极性溶液接触。 第一和第二下部电极彼此面对。 分离电极设置在电介质阻挡层的表面中。 分离电极包括布置在彼此面对的电介质阻挡层的表面中的第一和第二分离电极（36,37）。 第一和第二分离电极根据电介质屏障的高度方向被分成多个电极单元（361-36n，371-37n）。

公开(公告)号：KR1020080017614A

公开(公告)日：2008-02-27

申请号：KR1020060078910

申请日：2006-08-21

Applicant: 삼성전자주식회사

Inventor： 박재철 ,  박영수 ,  김선일

IPC: H01L29/786

CPC classification number: H01L29/66757 ,  H01L27/3244 ,  H01L29/41733 ,  H01L29/458

Abstract: A method for manufacturing a silicon thin film transistor is provided to prevent the damage of source and drain electrodes in a silicon surface treatment process. A silicon channel(12) is formed on a substrate(10). Two electrodes(14s,14d) are formed on both sides of the silicon channel. The electrodes are electrically connected to each other. A fluorine-treating process for an uncovered surface of the silicon channel is performed by using fluorine-based gas plasma. A gate insulating layer(15) is formed on a stacked structure including the silicon channel and the electrodes formed on both sides of the silicon channel. A gate electrode corresponding to the silicon channel is formed on the gate insulating layer.

Abstract translation: 提供一种制造硅薄膜晶体管的方法，以防止在硅表面处理过程中源电极和漏电极的损坏。 在衬底（10）上形成硅通道（12）。 两个电极（14s，14d）形成在硅通道的两侧。 电极彼此电连接。 通过使用氟系气体等离子体，进行硅通道的未覆盖面的氟处理工序。 栅极绝缘层（15）形成在包括硅沟道和形成在硅沟道两侧的电极的层叠结构上。 在栅极绝缘层上形成对应于硅沟道的栅电极。

公开(公告)号：KR1020060092396A

公开(公告)日：2006-08-23

申请号：KR1020050013140

申请日：2005-02-17

Applicant: 삼성전자주식회사

Inventor： 김선일

IPC: G02B1/02

CPC classification number: G02B1/02 ,  B81B3/0035 ,  G03F7/20

Abstract: 본 발명은 3차원 광결정(3D photonic crystal)을 제조하는 방법을 개시한다. 본 발명의 일 실시예에 따른 3차원 광결정 제조 방법은, 할로겐화은 미립자가 분산된 젤라틴을 기판 위에 도포하여 감광성 매질을 마련하는 단계; 반복적인 패턴을 갖는 3차원 간섭 무늬를 상기 감광성 매질 내에 발생시켜, 상기 감광성 매질을 상기 반복적인 3차원 패턴으로 노광시키는 단계; 상기 감광성 매질을 현상하여 노광 영역의 할로겐화은을 금속은으로 환원시키는 단계; 상기 현상된 감광성 매질을 표백하는 단계; 및 정착 공정을 통해 상기 표백된 감광성 매질 내의 은염을 제거하는 단계;를 포함하며, 상기 정착 공정 후에 감광성 매질 내의 비노광 영역에는 순수 젤라틴이 남고 노광 영역에는 미세 기공이 남는 것을 특징으로 한다.

公开(公告)号：KR1020060056469A

公开(公告)日：2006-05-25

申请号：KR1020040095559

申请日：2004-11-20

Applicant: 삼성전자주식회사

Inventor： 김선일 ,  한명환

IPC: H04B1/40

CPC classification number: G06F3/0481 ,  G06F3/0484 ,  H04M1/72563 ,  H04M1/72583

Abstract: 본 발명은 이동통신 단말기에서 배경화면 컨텐츠 정보의 위치를 이동시킬 수 있는 장치 및 방법을 제공한다. 이를 위해 본 발명에서는, 사용자가 배경화면 컨텐츠 정보의 위치 이동을 선택하였을 경우 현재 사용자가 선택한 배경화면 위에서 사용자의 입력에 따라 이동되는 배경화면 컨텐츠 정보의 위치를 디스플레이하고, 사용자가 저장을 선택하였을 경우 현재 표시부에 디스플레이되는 배경화면 컨텐츠 정보의 위치에 대한 정보를 저장한다. 그리고 상기 배경화면 컨텐츠 정보의 위치 정보에 따라 표시부에 디스플레이되는 배경화면 컨텐츠 정보가 이동되어 디스플레이될 수 있도록 한다. 이에 따라 사용자는 자신이 설정한 배경화면의 특정 부분이 상기 시계 및 대기 화면 문구를 포함하는 배경화면 컨텐츠 정보에 가려지지 않도록 할 수 있으므로, 사용자가 배경 화면 또는 배경화면 컨텐츠 정보에 따른 제약없이 사용자가 원하는 배경화면 또는 배경화면 컨텐츠 정보를 선택할 수 있도록 한다.
이동통신 단말기, 시계, 대기 화면 문구