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公开(公告)号：KR1020120031644A
公开(公告)日：2012-04-04
申请号：KR1020100093133
申请日：2010-09-27
Applicant: 삼성전기주식회사
IPC: G01R31/3183 , G01R31/28
CPC classification number: G01R31/318536
Abstract: PURPOSE: A boundary scan test apparatus and method of an embedded substrate are provided to improve reliability of function test about the embedded substrate by processing a boundary scan test about a semiconductor chip included in the embedded substrate. CONSTITUTION: A boundary scan test arrangement of an embedded substrate comprises a plurality of embedded substrates(1), a plurality of test chips(2), and a test controller(3). The embedded substrate includes a semiconductor chip which becomes an object for test. The test chip processes a boundary scan test about the semiconductor chip included in the embedded substrate. The test controller controls the test chip. The plurality of test chips is formed into a chain shape in which a test input terminal is connected to a test output terminal. A first probe is connected to a contact point of one side of the embedded substrate. A second probe is connected to a contact point of the other side of the embedded substrate.
Abstract translation: 目的：提供嵌入式基板的边界扫描测试装置和方法，通过处理包括在嵌入式基板中的半导体芯片的边界扫描测试来提高嵌入式基板的功能测试的可靠性。 构成：嵌入式基板的边界扫描测试装置包括多个嵌入式基板（1），多个测试芯片（2）和测试控制器（3）。 嵌入式基板包括成为测试对象的半导体芯片。 测试芯片对包含在嵌入式衬底中的半导体芯片进行边界扫描测试。 测试控制器控制测试芯片。 多个测试芯片形成为测试输入端子连接到测试输出端子的链状。 第一探针连接到嵌入式基板的一侧的接触点。 第二探针连接到嵌入式基板的另一侧的接触点。
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公开(公告)号：KR101085752B1
公开(公告)日：2011-11-21
申请号：KR1020100043490
申请日：2010-05-10
Applicant: 삼성전기주식회사
CPC classification number: G01R31/2818 , G01R31/2812 , H05K1/0268 , H05K1/185 , H05K2203/162
Abstract: PURPOSE: A circuit board and a method for testing component built in a circuit board are provided to distinguish the failure of a circuit board by testing a connection state even when an active device and a passive device are mounted therein. CONSTITUTION: In a circuit board and a method for testing component built in a circuit board, active circuit elements(102,104) are mounted inside a circuit substrate. Passive devices(106, 108, 110) electrically interlink a signal pad of the circuit board. Test pads(112, 114) electrically interlink to one end of the passive device.
Abstract translation: 目的：提供一种电路板和用于测试电路板内部组件的方法，以便即使当有源器件和无源器件安装在其中时也可以通过测试连接状态来区分电路板的故障。 构成：在电路板和用于测试内置于电路板中的部件的方法中，有源电路元件（102,104）安装在电路基板的内部。 无源器件（106,108,110）电连接电路板的信号焊盘。 测试焊盘（112,114）与无源器件的一端电连接。
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公开(公告)号：KR101077313B1
公开(公告)日：2011-10-27
申请号：KR1020090052477
申请日：2009-06-12
Applicant: 삼성전기주식회사
IPC: H05K1/18
Abstract: 본발명은전자부품내장형인쇄회로기판에관한것으로서, 지지테입상부에접속단자가형성된활성면이지지테입과접하도록전자부품을배치하고, 전자부품을감싸도록지지테입상부에절연층을적층한다음지지테입을제거하고절연층상에상기접속단자와전기적으로접속하는접속패턴을포함하는회로층을형성하는공정을포함하며, 전자부품을절연층내부에매립하기위해절연층에전자부품형성용공동을가공하는공정이삭제되므로공정비용을줄일수 있고제조시간을단축할수 있는장점이있다.
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公开(公告)号：KR101055432B1
公开(公告)日：2011-08-08
申请号：KR1020080107128
申请日：2008-10-30
Applicant: 삼성전기주식회사
CPC classification number: H01L24/83 , H01L2224/04105 , H01L2224/19 , H01L2224/83101 , H01L2224/18 , H01L2924/00012
Abstract: 본 발명은 정렬홀을 갖는 반도체칩 및 그 제조방법에 관한 것으로, 반도체칩의 외부접속범프의 위치정보를 갖는 정렬홀이 반도체칩에 형성됨으로써, 인쇄회로기판에 정렬이 된 상태에서 내장이 됨으로써 인쇄회로기판의 외층 회로층에 형성되는 비아와 정합하여 인쇄회로기판과의 전기 도통 성능이 향상되고 신뢰성이 향상되게 된다.
반도체칩, 정렬홀, 외부접속범프, 식각, 베리어층, 홈부, 웨이퍼-
公开(公告)号：KR1020110006525A
公开(公告)日：2011-01-20
申请号：KR1020090064200
申请日：2009-07-14
Applicant: 삼성전기주식회사
CPC classification number: H05K1/185 , H01L2224/04105 , H01L2224/16225 , H01L2224/2518 , H01L2924/19105 , H05K3/4602 , H05K3/465 , H05K3/4697
Abstract: PURPOSE: An electronic device built-in printed circuit board and a manufacturing method thereof are provided to reduce the time and const required for processing a cavity in a core substrate by forming a printed circuit board of high density which includes the electronic device. CONSTITUTION: A core substrate(10) passes through a cavity(12). A plurality of electric components(30, 40) is parallelly installed in the cavity. An insulating layer(18) is laminated on both sides of the core substrate. A circuit pattern is formed on the surface of the insulating layer. A plurality of bias(17) electrically connects the circuit pattern and the plurality of electric components.
Abstract translation: 目的：提供一种电子设备内置印刷电路板及其制造方法，以通过形成包括电子设备的高密度印刷电路板来减少处理芯基板中的空腔所需的时间和常数。 构成：芯基板（10）穿过空腔（12）。 多个电气部件（30,40）平行地安装在空腔中。 绝缘层（18）层叠在芯基板的两侧。 在绝缘层的表面上形成电路图案。 多个偏压（17）电连接电路图案和多个电气部件。
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Patent Agency Ranking
公开(公告)号：KR1020100133768A
公开(公告)日：2010-12-22
申请号：KR1020090052477
申请日：2009-06-12
Applicant: 삼성전기주식회사
IPC: H05K1/18
Abstract: PURPOSE: An electronic component embedded PCB and a manufacturing method thereof are provided to reduce processing costs by removing a process of processing a hole for the formation of an electronic part on an insulation layer. CONSTITUTION: An insulating layer(500) is made of an electrical insulation material. An electronic part(300) is buried to the insulating layer in order to combine an active surface having a connection terminal(310) with one surface of the insulating layer. A circuit layer is formed in one side of the insulating layer. The circuit layer comprises a connection pattern(710) which is electrically connected to the connection terminal. A build-up layer(800) is laminated on one side or both sides of the insulating layer. The build-up layer comprises a via which is electrically connected to the connection pattern and a circuit pattern(830).
Abstract translation: 目的：提供电子部件嵌入式PCB及其制造方法，以通过去除在绝缘层上形成电子部件的孔的处理过程来降低加工成本。 构成：绝缘层（500）由电绝缘材料制成。 将电子部件（300）埋入绝缘层中，以将具有连接端子（310）的有源表面与绝缘层的一个表面组合。 电路层形成在绝缘层的一侧。 电路层包括电连接到连接端子的连接图案（710）。 在绝缘层的一侧或两侧层叠积层（800）。 积聚层包括电连接到连接图案的通孔和电路图案（830）。
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公开(公告)号：KR100999531B1
公开(公告)日：2010-12-08
申请号：KR1020080102508
申请日：2008-10-20
Applicant: 삼성전기주식회사
CPC classification number: H05K1/185 , H01L21/6835 , H01L23/49827 , H01L23/5389 , H01L23/544 , H01L24/24 , H01L24/82 , H01L25/0655 , H01L25/0657 , H01L2223/54426 , H01L2224/04105 , H01L2224/2402 , H01L2224/24226 , H01L2224/24227 , H01L2225/06524 , H01L2225/06575 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H05K1/0269 , H05K3/305 , H05K3/386 , H05K3/4602 , H05K2201/0195 , H05K2201/09918 , H05K2201/10515 , H05K2203/063 , H05K2203/066 , Y10T156/1052
Abstract: 인쇄회로기판 및 그 제조방법이 개시된다. 접착층의 상면에 전자소자를 부착시키는 단계; 전자소자가 매립되도록, 전자소자의 상측 및 접착층의 하측에 절연체를 각각 적층하는 단계; 및 절연체에 회로패턴 및 비아를 형성하는 단계를 포함하는 인쇄회로기판 제조방법은, 접착층을 제거하지 않고 공정을 진행함으로써, 생산수율을 향상시킬 수 있다.
인쇄회로기판, 접착층, 캐비티, 전자소자-
公开(公告)号：KR100986829B1
公开(公告)日：2010-10-12
申请号：KR1020070113420
申请日：2007-11-07
Applicant: 삼성전기주식회사
IPC: H05K1/02
Abstract: 반도체칩 및 이를 이용한 인쇄회로기판의 제조방법이 개시된다. (a) 범프가 형성된 면의 가장자리에 댐(dam)이 형성된 반도체칩을 준비하는 단계, (b) 관통홀이 형성된 코어기판의 일면에 테이프를 부착하는 단계, (c) 상기 관통홀의 내부에 노출된 상기 테이프에 상기 범프가 형성된 방향으로 상기 반도체칩을 부착하는 단계, (d) 상기 코어기판의 타면에 제1 절연층을 적층하는 단계, (e) 상기 코어기판의 일면의 테이프를 제거하는 단계, 및 (f) 상기 코어기판의 일면에 제 2절연층을 적층하는 단계를 포함하는 인쇄회로기판의 제조방법이 제공된다.
반도체칩, 코어기판, 테이프, 절연층-
公开(公告)号：KR1020100048112A
公开(公告)日：2010-05-11
申请号：KR1020080107128
申请日：2008-10-30
Applicant: 삼성전기주식회사
CPC classification number: H01L24/83 , H01L2224/04105 , H01L2224/19 , H01L2224/83101 , H01L2224/18 , H01L2924/00012
Abstract: PURPOSE: A semiconductor chip including an alignment hole and a method for manufacturing the same are provided to improve the electro connection performance between the semiconductor chip and a printed circuit board by forming the alignment hole with location information of an external connection bump. CONSTITUTION: An external connection bump(130) is formed on one side of a semiconductor chip(100A). The external connection bump draws the signal of an electronic circuit which is integrated to the semiconductor chip. An alignment hole(102B) passes through the semiconductor chip and includes the location information of the external connection bump. The alignment hole is formed on the center of the semiconductor chip.
Abstract translation: 目的：提供一种包括对准孔的半导体芯片及其制造方法，用于通过形成具有外部连接凸块的位置信息的对准孔来改善半导体芯片与印刷电路板之间的电连接性能。 构成：在半导体芯片（100A）的一侧上形成外部连接凸块（130）。 外部连接凸块画出集成到半导体芯片的电子电路的信号。 对准孔（102B）穿过半导体芯片并且包括外部连接凸块的位置信息。 对准孔形成在半导体芯片的中心。
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公开(公告)号：KR1020090117237A
公开(公告)日：2009-11-12
申请号：KR1020080043185
申请日：2008-05-09
Applicant: 삼성전기주식회사
IPC: H05K1/18
CPC classification number: H05K1/185 , H01L21/568 , H01L23/5389 , H01L24/19 , H01L24/82 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73267 , H01L2224/92144 , H01L2224/92244 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H05K3/025 , H05K3/4602 , H05K2201/10674 , H05K2203/0152 , H05K2203/063 , H05K2203/1152 , H05K2203/1469 , Y10T29/49124 , Y10T29/4913 , H01L2924/00
Abstract: PURPOSE: An electronic device-embedded printed circuit board and a manufacturing method thereof are provided to simplify a process without a process for forming an additional insulation layer by directly laminating a resin layer on a core layer. CONSTITUTION: An electronic device(20) is embedded in a core layer(30). A resin layer(13) is formed in the core layer. The core layer includes prepreg. An inner layer circuit(50) is formed on the resin layer by an SAP(Semi-Additive Process) or an MSAP(Modified Semi-Additive Process). The inner layer circuit is electrically connected to the electronic device. An insulation layer(60) is formed on the inner layer circuit. An outer layer circuit(70) is formed on the insulation layer. The outer layer circuit is connected to the inner layer circuit.
Abstract translation: 目的：提供一种电子器件嵌入式印刷电路板及其制造方法，以通过在芯层上直接层叠树脂层来简化不用形成附加绝缘层的工艺的工艺。 构成：电子器件（20）嵌入在芯层（30）中。 在芯层中形成树脂层（13）。 芯层包括预浸料。 通过SAP（半添加剂法）或MSAP（改性半添加法）在树脂层上形成内层电路（50）。 内层电路电连接到电子设备。 绝缘层（60）形成在内层电路上。 在绝缘层上形成外层电路（70）。 外层电路连接到内层电路。
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