公开(公告)号：KR1020040052014A

公开(公告)日：2004-06-19

申请号：KR1020020079732

申请日：2002-12-13

Applicant: 한국전자통신연구원

Inventor： 김상필 ,  조한진

IPC: G06F17/50

Abstract: PURPOSE: A system for managing a semiconductor design tool and a managing method using the same are provided to save an expense by preventing a manager from wasting time and manpower through integrated management. CONSTITUTION: An integrated design environment management tool(100) responds to a request for using the design tool of each user(170) and displays various functions of the design tool by keeping the distributed design tool information. A database group(150) provides various kinds of information databased by the integrated design environment management tool. The integrated design environment management tool displays various functions and a response to the user by equipping with a monitoring tool. The database group includes user information, design tool information, host information, and license information stored in each database.

Abstract translation: 目的：提供一种用于管理半导体设计工具的系统和使用其的管理方法，以通过防止管理者通过综合管理浪费时间和人力来节省费用。 构成：集成设计环境管理工具（100）响应使用每个用户（170）的设计工具的请求，并通过保留分布式设计工具信息显示设计工具的各种功能。 数据库组（150）提供由综合设计环境管理工具数据库提供的各种信息。 集成设计环境管理工具通过配备监控工具显示各种功能和对用户的响应。 数据库组包括存储在每个数据库中的用户信息，设计工具信息，主机信息和许可证信息。

公开(公告)号：KR100436434B1

公开(公告)日：2004-06-16

申请号：KR1020010071757

申请日：2001-11-19

Applicant: 한국전자통신연구원

Inventor： 전인산 ,  김혁 ,  양우석 ,  김경수 ,  김환우 ,  조한진

IPC: H03M13/37

CPC classification number: H03M13/3922 ,  H03M13/2957 ,  H03M13/6502 ,  H03M13/6505

Abstract: The present invention relates to a turbo decoder having a state metric, a calculating method using the turbo decoder and a computer-readable recoding medium for executing a calculation method implemented to the turbo decoder. The turbo decoder includes branch metric calculation unit, state metric calculation unit and log likelihood ratio calculation unit. The present invention may reduce calculation steps by simplifying a conventional turbo decode algorithm, reducing a size of a hardware, which the turbo decoder can be implemented in as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The present invention can be implemented in an error correction in wireless communication system and satellite communication system.

Abstract translation: 本发明涉及具有状态度量的turbo解码器，使用turbo解码器的计算方法和用于执行对turbo解码器实现的计算方法的计算机可读记录介质。 turbo解码器包括分支度量计算单元，状态度量计算单元和对数似然比计算单元。 本发明可以通过简化传统的turbo解码算法，减小硬件的大小来减少计算步骤，turbo解码器可以作为专用集成电路（ASIC）或现场可编程门阵列（FPGA）实现。 本发明可以用无线通信系统和卫星通信系统中的纠错来实现。

公开(公告)号：KR1020040048471A

公开(公告)日：2004-06-10

申请号：KR1020020076202

申请日：2002-12-03

Applicant: 한국전자통신연구원

Inventor： 김원종 ,  김승철 ,  조한진 ,  이광엽

IPC: G06F7/52

CPC classification number: G06F7/724

Abstract: PURPOSE: A serial finite field multiplier is provided to minimize the consumption power and a size of a multiplying circuit needed for the high polynomial finite field multiplication by forming a register with a latch, and controlling an order for shifting a clock and the data. CONSTITUTION: The first shift register(11) shifts the first input value to right by one bit depending on the first and the third clock. The second shift register(12) shifts the second input value to right by one bit depending on the first and the third clock. Logic gates perform the AND operation for the first and the second input value of each bit. The register(13) generates/stores a multiplication result by adding an output value of each logic gate to a value of each bit.

Abstract translation: 目的：提供串行有限域乘法器，以通过与锁存器形成寄存器来最小化高多项式有限域乘法所需的乘法电路的消耗功率和大小，并且控制用于移位时钟和数据的顺序。 构成：根据第一和第三个时钟，第一个移位寄存器（11）将第一个输入值向右移位一位。 第二移位寄存器（12）根据第一和第三时钟将第二输入值向右移位一位。 逻辑门对每个位的第一和第二输入值执行AND运算。 寄存器（13）通过将每个逻辑门的输出值加到每个位的值来产生/存储相乘结果。

公开(公告)号：KR1020040048006A

公开(公告)日：2004-06-07

申请号：KR1020020075752

申请日：2002-12-02

Applicant: 한국전자통신연구원

Inventor： 이미영 ,  박성모 ,  조한진

IPC: H04N7/24 ,  H04N21/236 ,  G06T7/20

Abstract: PURPOSE: A frame generator and a frame generating method using the frame generator are provided to generate a frame through a simple linear interpolation using preceding and following frames updated to have the same size. CONSTITUTION: Arbitrary shape VOPs decoded by an arbitrary shape decoder(101) are stored in a preceding frame buffer(105) and a following frame buffer(104). The VOPs stored in the preceding and following frame buffers are input to an arbitrary shape frame matching unit(102). When the two frames stored in the two frame buffers are different from each other, a matching point of the two frames is found through frame matching using an alpha map, and the matching point, a mode value, a maximum width and maximum length of the two frames are output to an arbitrary shape frame updating unit(103). The frame updating unit updates the VOPs using data of the preceding and following buffers and stores the updated VOPs in a temporary buffer(107).

Abstract translation: 目的：提供帧生成器和使用帧生成器的帧生成方法，以通过简单的线性插值来生成帧，其中前后帧被更新为具有相同的大小。 构成：由任意形状解码器（101）解码的任意形状的VOP被存储在前一帧缓冲器（105）和随后的帧缓冲器（104）中。 存储在前一帧和后续帧缓冲器中的VOP被输入到任意形状的帧匹配单元（102）。 当存储在两个帧缓冲器中的两个帧彼此不同时，通过使用α映射的帧匹配来找到两个帧的匹配点，并且匹配点，模式值，最大宽度和最大长度 两帧被输出到任意形状帧更新单元（103）。 帧更新单元使用先前和后续缓冲器的数据来更新VOP，并将更新的VOP存储在临时缓冲器（107）中。

公开(公告)号：KR100434111B1

公开(公告)日：2004-06-04

申请号：KR1020010085163

申请日：2001-12-26

Applicant: 한국전자통신연구원

Inventor： 김원종 ,  배영환 ,  조한진

IPC: G06F7/58

Abstract: PURPOSE: A pseudo random number generation system and a method for the same are provided to input a seed value necessary for a random number generation or to store previously generated random numbers, and to generate random numbers by using the seed value or the stored random numbers so that it is difficult to predict the generated random numbers. CONSTITUTION: The system comprises a clock generator(2), a shift register(1), a seed value storage(4), and an operation controller(3). The clock generator(2) supplies the clock signals necessary for the random number generation. The shift register(1) generates the random numbers by changing the stored seed value according to the supplied clock signals, and outputs the random numbers to an external device. The seed value storage(4) stores an initial value and the random numbers output by the shift register(1), uses the stored random numbers as seed values, and supplies the seed values for the shift register(1). The operation controller(3) controls the operation of the clock generator(2), the shift register(1) and the seed value storage(4).

Abstract translation: 目的：提供一种伪随机数生成系统及其方法，以输入随机数生成所需的种子值或存储先前生成的随机数，并通过使用种子值或所存储的随机数生成随机数 所以很难预测产生的随机数。 构成：该系统包括时钟发生器（2），移位寄存器（1），种子值存储器（4）和操作控制器（3）。 时钟发生器（2）提供随机数发生所需的时钟信号。 移位寄存器（1）通过根据所提供的时钟信号改变所存储的种子值来生成随机数，并将该随机数输出到外部装置。 种子值存储部（4）存储由移位寄存器（1）输出的初始值和随机数，将所存储的随机数作为种子值，供给移位寄存器（1）的种子值。 操作控制器（3）控制时钟发生器（2），移位寄存器（1）和种子值存储器（4）的操作。

公开(公告)号：KR100392258B1

公开(公告)日：2003-07-22

申请号：KR1020010011086

申请日：2001-03-05

Applicant: 한국전자통신연구원

Inventor： 변경진 ,  최민석 ,  김경수 ,  조한진

IPC: G10L19/12 ,  G10L19/16

Abstract: PURPOSE: An encoding and decoding block structure for reducing process delay time of a CELP vocoder and an encoding and decoding method using the structure are provided to divide an encoding block into sub-modules to process the encoding block to decrease the entire delay time of a system. CONSTITUTION: An encoding block is divided into a plurality of sub-modules(31) having a predetermined quantity of calculation corresponding to encoding process delay time determined in one frame, and encoding is executed for each of the sub-modules. A decoding block is divided into sub-frames(32) that are determined based on one frame between the sub-modules, and decoding is carried out by the sub-frames. When process delay time of one frame is 20ms, the encoding block is divided into eight sub-modules each of which has the processing time of 2ms, and the decoding block is divided into four sub-frames each of which has the processing time of 1ms. A sound signal is encoded and decoded through the encoding and decoding block.

Abstract translation: 目的：提供一种用于减少CELP声码器的处理延迟时间的编码和解码块结构以及使用该结构的编码和解码方法，以将编码块划分为子模块以处理编码块以减小 系统。 组成：编码块被分成多个子模块（31），其具有与在一帧中确定的编码处理延迟时间相对应的预定数量的计算，并且对每个子模块执行编码。 解码块被划分成基于子模块之间的一个帧确定的子帧（32），并且通过子帧执行解码。 当一帧的处理延迟时间为20ms时，编码块被分成八个子模块，每个子模块具有2ms的处理时间，并且解码块被分成四个子帧，每个子帧具有处理时间为1ms 。 声音信号通过编码和解码块进行编码和解码。

公开(公告)号：KR1020030056565A

公开(公告)日：2003-07-04

申请号：KR1020010086827

申请日：2001-12-28

Applicant: 한국전자통신연구원

Inventor： 배영환 ,  장준영 ,  조한진 ,  류광기

IPC: H04L29/06

Abstract: PURPOSE: An algorithm generating an interface between IP(Intellectual Property) module is provided to achieve an interface synthesizer used in an actual design. CONSTITUTION: An operation of an interface module is inputted using a timing diagram editor. A signal transition graph(STG) is generated by reading the above timing diagram information(2). A finite state machine(FSM) is generated from the signal transition graph(3). The number of states is minimized by merging states which are merged from the above finite state machine(4). The generated finite state machine is output in the type of a state transition table or VHDL program. And the state transition table and the VHDL program are synthesized using a logic synthesizer.

Abstract translation: 目的：提供一种生成IP（知识产权）模块之间接口的算法，以实现实际设计中使用的接口合成器。 构成：使用时序图编辑器输入接口模块的操作。 通过读取上述时序图信息（2）来生成信号转换图（STG）。 从信号转换图（3）生成有限状态机（FSM）。 通过从上述有限状态机（4）合并的合并状态来最小化状态数。 生成的有限状态机以状态转换表或VHDL程序的类型输出。 并且使用逻辑合成器来合成状态转换表和VHDL程序。

公开(公告)号：KR100365724B1

公开(公告)日：2002-12-31

申请号：KR1020000083169

申请日：2000-12-27

Applicant: 한국전자통신연구원

Inventor： 김혁 ,  전인산 ,  양우석 ,  김경수 ,  조한진

IPC: H03M13/37

Abstract: 본 발명은 이진 로그맵 알고리즘(Binary LogMAP Algorithm)을 이용한 터보 복호기 및 그 구현 방법과 상기 방법을 실현시키기 위한 프로그램을 기록한 컴퓨터로 읽을 수 있는 기록매체에 관한 것으로, 이진 LogMAP 알고리즘을 사용하여 터보 복호기를 구현하는 경우에, 기존의 LogMAP 알고리즘에서 사용되었던 복잡한 E 함수를 대신하여, 하드웨어의 구현이 용이한 2 함수를 사용하며, 이의 계산에 ABELA를 적용하여 작은 하드웨어를 가지면서도 정밀도가 높은 복호기를 구현할 수 있으며, 또한 순방향 및 역방향 상태 메트릭 값의 계산에 있어서 필요한 연산량을 줄이고 LLR의 계산을 고속으로 수행할 수 있어 기존의 LogMAP 방식의 터보 복호기에 비하여 작은 하드웨어를 필요로 하면서도 고속의 복호가 가능한 터보 복호기를 구현할 수 있다.

公开(公告)号：KR100355266B1

公开(公告)日：2002-10-11

申请号：KR1020000057316

申请日：2000-09-29

Applicant: 한국전자통신연구원

Inventor： 이호석 ,  어익수 ,  김경수 ,  조한진

IPC: H04B1/709 ,  H04J13/20

Abstract: 본 발명은 확산 스펙트럼 통신용 복조기에 사용될 수 있는 상관기에 관한 것으로, 확산 스펙트럼 통신용 신호 복조에 사용되는 복조기가 STTD 디코딩을 지원할 수 있도록 복조기 내에 STTD 디코더가 포함되어 있으며, 상기 STTD 디코더는 하나의 곱셈기와 하나의 적분기를 사용함으로서 배치면적이 작고, STTD 모드인지 아닌지에 따라 STTD 디코더의 동작을 간단히 조절할 수 있어 가변신호처리에도 적합한 것을 특징으로 한다.

公开(公告)号：KR1020020053978A

公开(公告)日：2002-07-06

申请号：KR1020000082253

申请日：2000-12-26

Applicant: 한국전자통신연구원

Inventor： 한경태 ,  임인기 ,  어익수 ,  서혜주 ,  김경수 ,  정희범 ,  조한진

IPC: H04B1/16

CPC classification number: H04L5/06 ,  H04B1/7115

Abstract: PURPOSE: A carrier separating apparatus and method of a multi-carrier radio communication receiving system are provided to reduce the number of quantizers by separating carriers after its quantization, and easily control power of a carrier by equalizing a frequency power of each carrier by rendering the number of frequency down adjustments to be the same. CONSTITUTION: An internal oscillation(NCO) block(210) generates internal multi-carriers in order to separate the multi-carriers from a received signal. A multiplier block(240) down-converts each of the multi-carriers generated by the internal oscillation(NCO) block(210) and moves them to a frequency of 0. A low frequency band pass filter block(250) filters each carrier moved to the frequency of 0 by the multiplier block(240) to a low frequency pass band to delete information of an unnecessary band and provides its own carrier information as an input of a rake receiver(300).

Abstract translation: 目的：提供一种多载波无线电通信接收系统的载波分离装置和方法，通过在量化后分离载波来减少量化器的数量，并且通过使每个载波的频率功率均衡，容易地控制载波的功率 频率下降调整数相同。 构成：内部振荡（NCO）块（210）产生内部多载波，以便将多载波与接收信号分离。 乘法器块（240）对由内部振荡（NCO）块（210）产生的多个载波进行下变频，并将它们移动到0的频率。低频带通滤波器块（250）对每个载波移动 通过乘法器块（240）将频率为0的频率转换为低频通带，以删除不需要的频带的信息，并提供其自己的载波信息作为前置雷达接收机（300）的输入。