公开(公告)号：WO1998012753A1

公开(公告)日：1998-03-26

申请号：PCT/US1997005826

申请日：1997-05-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WOLLESEN, Donald, L. ,  FATEMI, Homi

IPC: H01L29/423

CPC classification number: H01L29/78 ,  H01L29/456 ,  H01L29/49 ,  H01L29/66621

Abstract: A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (Leff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom. Because of the V-shaped structure of the gate, the effective saturated length of the channel with drain voltage applied only extends from the edge of the source to just prior to the tip of the V-shaped structure in the interior of the semiconductor substrate. The drain side of the V-shaped structure becomes a depletion region due to the applied drain voltage. Due to this characteristic of such a structure, the surface width of the gate can be, for example, two or more times the distance of the desired channel length thereby permitting conventional lithography to be used to define the gate lengths much shorter than the lithographic limit.

Abstract translation: 在半导体衬底中形成具有V形壁的沟槽或沟槽栅极的场效应晶体管，并且在V形壁上生长栅极氧化物到衬底表面，并且填充有诸如多晶硅的栅电极材料。 优选地，在填充沟槽之前，V形壁的底部是圆形的。 源极/漏极杂质可以扩散或注入到V形栅极的表面氧化物两侧的衬底区域中。 触点在场隔离中被制成源极，漏极和栅极，以完成结构。 所得到的FET结构包括具有常规源极和漏极的自对准V形栅极，该源极和漏极被场隔离包围，但具有小于栅极表面宽度的约一半的有效沟道长度（Leff）。 优选地，V形门的会聚壁在圆形凹入的底部中。 由于栅极的V形结构，所以施加漏极电压的沟道的有效饱和长度仅从源极的边缘延伸到半导体衬底内部的V形结构的尖端之前。 V形结构的漏极侧由于施加的漏极电压而变为耗尽区。 由于这种结构的这种特性，栅极的表面宽度可以是例如期望沟道长度的两倍或更多倍的距离，从而允许常规光刻用于限定比光刻极限短的栅极长度 。

公开(公告)号：WO1998011701A1

公开(公告)日：1998-03-19

申请号：PCT/US1997003539

申请日：1997-03-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CRAYFORD, Ian, Stephen ,  SIVAKOLUNDU, Ramesh

IPC: H04L29/06

CPC classification number: H04L61/2038 ,  G06F12/0661 ,  H04L12/44 ,  H04L29/12254 ,  H04L29/12801 ,  H04L29/12839 ,  H04L61/6004 ,  H04L61/6022

Abstract: Dynamic assignation of addresses to multiple PHY devices by a management station coupled to each of the PHY devices permits the management station to uniquely address each PHY device without a priori knowledge of the PHY addresses. The addresses are assigned by the station which thereby knows the addresses to use to access specific PHY devices.

Abstract translation: 通过耦合到每个PHY设备的管理站向多个PHY设备的地址的动态分配允许管理站在没有PHY地址的先验知识的情况下唯一地寻址每个PHY设备。 地址由站分配，由此知道用于访问特定PHY设备的地址。

公开(公告)号：WO1998011696A1

公开(公告)日：1998-03-19

申请号：PCT/US1997006888

申请日：1997-04-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  RUNALDUE, Thomas, Jefferson ,  KADAMBI, Jayant

IPC: H04L12/44

CPC classification number: H04L49/351

Abstract: The present invention comprises a system and method for reducing the pin count between a plurality of MAC and PHY devices within a switching element. In this embodiment, the switching element includes a plurality of general serial interfaces for providing connections between respective MAC and PHY devices and each of the plurality of general serial interfaces operates at a first data rate. The system and method comprises a multiplexer coupled to the plurality of general serial interfaces and a pad member including a plurality of pins. The pad member is coupled to the multiplexer and receives multiplexed signals from the plurality of general serial interfaces. The multiplexer operates at a second data rate that is a multiple of the first data rate. Generally, a system and method in accordance with the present invention allows for the multiplexing of a general purpose serial interface (GPSI) to reduce the pin count in some cases by as much as 75 % and also synchronize the MAC/PHY interface. In this example, the multiplexer interface uses a total of 7 pins and supports a total of four MAC/PHY connections. If only GPSIs were utilized, 28 pins would be required for this function. The same multiplexing technique will also reduce the MAC/PHY interface in four 100Mbps connections from 56 pins for a four port system to 18 pins. In each example the multiplexer interface will operate at four times the speed of the general serial interface.

Abstract translation: 本发明包括用于减少开关元件内的多个MAC和PHY器件之间的引脚计数的系统和方法。 在该实施例中，开关元件包括多个通用串行接口，用于提供相应MAC和PHY设备之间的连接，并且多个通用串行接口中的每一个以第一数据速率工作。 该系统和方法包括耦合到多个通用串行接口的多路复用器和包括多个引脚的焊盘构件。 焊盘构件耦合到多路复用器，并从多个通用串行接口接收复用的信号。 多路复用器以第一数据速率的倍数的第二数据速率操作。 通常，根据本发明的系统和方法允许多路复用通用串行接口（GPSI），以在一些情况下减少引脚数量高达75％，并且还使MAC / PHY接口同步。 在这个例子中，多路复用器接口共使用7个引脚，并且总共支持4个MAC / PHY连接。 如果仅使用GPSI，则此功能将需要28个引脚。 相同的复用技术还将减少四个100Mbps连接中的MAC / PHY接口，从56个引脚到四个端口系统到18个引脚。 在每个示例中，多路复用器接口将以通用串行接口的四倍速度运行。

公开(公告)号：WO1998011692A1

公开(公告)日：1998-03-19

申请号：PCT/US1997006325

申请日：1997-04-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GROSSMAN, Leonid ,  VEPA, Ramakrishna

IPC: H04L12/26

CPC classification number: H04L43/16 ,  H04L12/40032 ,  H04L43/0811 ,  H04L43/0823

Abstract: A method for identifying an error condition due to a faulty cable connection in a network comprising a plurality of computer systems, at least one of the computer systems including a network adapter with the network adapter including a media access control (MAC) unit, includes initializing a plurality of mechanisms for tracking a plurality of conditions in the MAC of the network adapter. The method further includes receiving a transmit demand request in the network adapter and updating the plurality of mechanisms according to a current status of each of the plurality of conditions. In addition, the method includes determining whether a predetermined threshold has been reached in one or more of the plurality of mechanisms, wherein when one or more of the plurality of mechanisms has reached the predetermined threshold, a faulty cable connection is identified. In a system aspect, the system includes a plurality of counting means for tracking each of a plurality of error conditions. The system further includes a media access control (MAC) unit for differentiating each of the plurality of error conditions. In addition, the system includes an error identification means for determining when any of the plurality of counting means has reached a predetermined threshold.

Abstract translation: 一种用于识别由包括多个计算机系统的网络中的有故障的电缆连接引起的错误状况的方法，所述计算机系统中的至少一个包括具有包括媒体访问控制（MAC）单元的网络适配器的网络适配器，包括初始化 用于跟踪网络适配器的MAC中的多个条件的多个机制。 该方法还包括在网络适配器中接收发送请求请求，并根据多个条件中的每一个的当前状态来更新多个机制。 此外，该方法包括确定在多个机构中的一个或多个机构中是否已经达到预定阈值，其中当多个机构中的一个或多个已经达到预定阈值时，识别出有故障的电缆连接。 在系统方面，该系统包括用于跟踪多个错误状况中的每一个的多个计数装置。 该系统还包括用于区分多个错误条件中的每一个的媒体访问控制（MAC）单元。 此外，该系统包括用于确定多个计数装置何时已经达到预定阈值的错误识别装置。

公开(公告)号：WO1998011486A1

公开(公告)日：1998-03-19

申请号：PCT/US1997016261

申请日：1997-09-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SCHMIDT, Rodney ,  ENNIS, Steve ,  WISOR, Michael, T.

IPC: G06F11/26

CPC classification number: G06F11/2231 ,  G06F11/2221 ,  G06F11/261

Abstract: A multiprocessing system comprising a plurality of processors and a plurality of I/O devices. A central interrupt control unit functionally intercouples the plurality of processors and I/O devices. The central interrupt control unit is configured to receive interrupt signals from the I/O devices and is configured to distribute interrupt signals to the processors. One of the processors is configured as a master test processor to control a test mode for testing the central interrupt control unit. The master test processor is further configured to release the other processors and emulate a multiprocessing environment.

Abstract translation: 一种包括多个处理器和多个I / O设备的多处理系统。 中央中断控制单元功能性地互连多个处理器和I / O设备。 中央中断控制单元被配置为从I / O设备接收中断信号，并且被配置为将中断信号分配给处理器。 其中一个处理器被配置为主测试处理器，以控制用于测试中央中断控制单元的测试模式。 主测试处理器还被配置为释放其他处理器并且模拟多处理环境。

公开(公告)号：WO1998010464A1

公开(公告)日：1998-03-12

申请号：PCT/US1997004986

申请日：1997-03-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HAO, Ming-Yin ,  OGLE, Robert, B., Jr. ,  WRISTERS, Derick

IPC: H01L21/28

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

Abstract: A process for growing an ultra-thin dielectric layer for use as a MOSFET gate oxide or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density of electron traps, and impedes dopant impurity diffusion from/to the dielectric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.

Abstract translation: 描述了用于生长用作MOSFET栅极氧化物或用于EEPROM的隧道氧化物的超薄介电层的工艺。 通过一氧化氮和一氧化二氮气体中的一系列退火形成氮氧化物层，其在晶圆 - 氧氮化物界面处和氧氮化物表面处的氮浓度具有峰值，并且在氮氧化物本体中具有低氮浓度。 该方法提供精确的厚度控制，改进的界面结构，电子陷阱的低密度，并阻止从介质和衬底扩散掺杂剂杂质。 该过程很容易集成到现有的制造过程中，并且增加了很少的成本。

公开(公告)号：WO1998008253A1

公开(公告)日：1998-02-26

申请号：PCT/US1997009424

申请日：1997-05-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I.

IPC: H01L21/8234

CPC classification number: H01L27/0922 ,  H01L21/823857

Abstract: A semiconductor manufacturing process for producing MOS integrated circuits having two gate oxide thicknesses. A first gate dielectric is formed on an upper surface of a semiconductor substrate. Thereafter, a masking layer is deposited on the first dielectric layer and patterned such that the first dielectric layer is exposed above a second region of the semiconductor substrate. The semiconductor wafer is then subjected to a thermal oxidation process such that a second gate dielectric is formed within the exposed second region of the semiconductor substrate. The second gate dielectric preferably has an oxide thickness that is unequal to the oxide thickness of the first gate dielectric layer. Thereafter, gate structures and source/drain structures are fabricated such that the integrated circuit includes a first transistor having a first gate dielectric thickness and a second transistor having a second gate dielectric thickness. In this manner, the integrated circuit can include selected transistors having a thinner gate dielectric for improving the performance of these selected transistors. In one embodiment, the n-channel transistors in a CMOS integrated circuit have a thinner gate oxide than the p-channel devices.

Abstract translation: 一种用于制造具有两个栅极氧化物厚度的MOS集成电路的半导体制造工艺。 第一栅极电介质形成在半导体衬底的上表面上。 此后，在第一电介质层上沉积掩模层并图案化，使得第一电介质层暴露在半导体衬底的第二区域之上。 然后对半导体晶片进行热氧化处理，使得第二栅极电介质形成在半导体衬底的暴露的第二区域内。 第二栅极电介质优选具有不等于第一栅极介电层的氧化物厚度的氧化物厚度。 此后，制造栅极结构和源极/漏极结构，使得集成电路包括具有第一栅极电介质厚度的第一晶体管和具有第二栅极电介质厚度的第二晶体管。 以这种方式，集成电路可以包括具有较薄栅极电介质的选择的晶体管，以改善这些选择的晶体管的性能。 在一个实施例中，CMOS集成电路中的n沟道晶体管具有比p沟道器件更薄的栅极氧化物。

公开(公告)号：WO1998007106A1

公开(公告)日：1998-02-19

申请号：PCT/US1997013983

申请日：1997-08-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  JONES, Robert, F., Jr.

IPC: G06F17/50

CPC classification number: G01R31/31858 ,  G06F17/5031

Abstract: Critical speed paths through a latch-based logic circuit must contain at least one latch-to-latch combinational delay which exceeds the nominal phase time of the circuit. To identify this set of paths through latch-to-latch delays greater than the nominal phase time of the circuit (i.e., through interesting tLLs), a half-path joining approach is employed. Backward half-paths from fixed timing points forward through the network defined by a latch abstraction of the circuit to an interesting tLL are multiplicatively joined with forward half-paths from the interesting tLL forward to other fixed timing points to form a set of fixed-point-to-fixed-point (F2F) paths through the interesting tLL. Timing analysis is performed on the set of F2F paths to identify those which represent critical speed paths through the circuit. The half-path joining approach is improved by performing timing analysis on the half-paths prior to combining. Based on the results of half-path timing analysis, the number of half-paths, and therefore the number of F2F paths resulting from a multiplicative joining of half-paths, is greatly reduced. One approach is to discard any half-path which is guaranteed to meet a target frequency. An enhancement is to identify at most two backward and two forward half-paths by identifying the worst half-path in each direction based on optimistic and pessimistic assumptions concerning time borrowing across the join point. A further enhancement is to perform only the pessimistic timing analysis. Although the purely pessimistic approach tends to favor failing path segments near the join point, any failing path segment which is "missed" because of the optimization is guaranteed to be found in another timing check because the "missed" segment must itself contain an interesting tLL.

Abstract translation: 通过基于锁存器的逻辑电路的临界速度路径必须包含至少一个超过电路额定相位时间的锁存器与锁存器组合延迟。 为了通过大于电路的标称相位时间（即，通过有趣的tLL）的锁存器到锁存器延迟来识别该组路径，采用半路连接方法。 从固定定时点向前通过由电路的锁存抽象定义为有趣的tLL的网络的向后半路径与从有趣的tLL向前到其他固定定时点的正向半路径被乘法连接，以形成一组定点 到定点（F2F）路径通过有趣的tLL。 对F2F路径进行定时分析，以识别代表通过电路的临界速度路径的定时分析。 通过在组合之前对半路径执行定时分析来改善半路连接方法。 基于半路时序分析的结果，半路径的数量以及因此半路径的乘法连接导致的F2F路径的数量大大减少。 一种方法是丢弃保证满足目标频率的任何半路。 增强是基于关于通过连接点的时间借用的乐观和悲观的假设，通过识别每个方向上最差的半路径来识别至多两个向后和两个前向半径。 进一步的增强是仅执行悲观的时间分析。 虽然纯粹悲观的方法倾向于偏向连接点附近的路径段失败，但是由于优化而被“遗漏”的任何故障路径段都被确保在另一个定时检查中被找到，因为“错过的”段必须包含有趣的tLL 。

公开(公告)号：WO1998005027A1

公开(公告)日：1998-02-05

申请号：PCT/US1997009220

申请日：1997-05-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HEWITT, Larry

IPC: G10H07/00

CPC classification number: G10H7/002 ,  G10H2230/031 ,  G10H2240/275

Abstract: A wavetable cache for an audio synthesizer which synthesizes music signal from voice data in a pooled memory uses a vertical architecture cache to communicate data from the memory to an audio signal processor. The vertical architecture cache includes a substantially limited number of queues, corresponding to only a fraction of the voices stored in the main memory and processed in the audio signal processor. A plurality of samples are transferred in a batch mode from the memory via a system bus to a queue. The samples are subsequently processed and accumulated for the entire plurality of samples by the audio signal processor. The limited number of queues are shared among the different voices in a round-robin fashion.

Abstract translation: 用于合成来自合并的存储器中的语音数据的音乐信号的音频合成器的波形缓存器使用垂直架构高速缓存来将数据从存储器传送到音频信号处理器。 垂直架构高速缓存包括基本上有限数量的队列，对应于仅存储在主存储器中并在音频信号处理器中处理的语音的一小部分。 多个样本以批处理模式从存储器经由系统总线传送到队列。 随后通过音频信号处理器对样本进行整个多个样本的处理和累积。 有限数量的队列以循环方式在不同的声音之间共享。

公开(公告)号：WO1998003993A1

公开(公告)日：1998-01-29

申请号：PCT/US1997008817

申请日：1997-05-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HAUSE, Fred, N. ,  GARDNER, Mark, L. ,  DAWSON, Robert

IPC: H01L21/768

CPC classification number: H01L21/76816

Abstract: A semiconductor process for forming an interlevel contact. A semiconductor wafer (100) is provided with a semiconductor substrate, a first conductive layer (102) formed on the substrate, and a dielectric layer (104) formed on the conductive layer. A border layer (106), preferably comprised of polysilicon nitride is formed on the dielectric layer (104). Portions of the border layer are then selectively removed to expose an upper surface region (110) of the dielectric layer, the selective removal of the border layer (106) resulting in a border layer having an annular sidewall extending upward from the dielectric layer (104) and encircling the spacer region (110). A spacer structure (116) is then formed on the annular sidewall, preferably, the spacer structure is formed by chemically vapor depositing a spacer material and anisotropically etching the spacer material to just clear in the planar regions with minimum overetch. The spacer structure (116) thereby covering peripheral portions of the spacer region such that an upper surface of a contact region remains exposed. Portions of the dielectric layer within the contact region are then removed to form a via (128) extending from an upper surface of the spacer structure to an upper surface of the first conductive layer. Preferably, the lateral dimension of the spacer regions (110) is approximately equal to the minimum feature size of a photolithography exposure apparatus in the lateral dimension of the via (120) at substantially less than the minimum feature size of the photolithography exposure apparatus.

Abstract translation: 一种用于形成层间接触的半导体工艺。 半导体晶片（100）设置有半导体衬底，形成在衬底上的第一导电层（102）和形成在导电层上的电介质层（104）。 在电介质层（104）上形成优选由多晶氮化物构成的边界层（106）。 然后选择性地去除边界层的部分以暴露电介质层的上表面区域（110），选择性地去除边界层（106），导致边界层具有从电介质层（104）向上延伸的环形侧壁 ）并且环绕间隔区（110）。 然后在环形侧壁上形成间隔结构（116），优选地，通过化学气相沉积间隔物材料并且各向异性地蚀刻间隔物材料形成间隔物结构，以在具有最小过蚀刻的平面区域中刚好清除。 间隔结构（116）由此覆盖间隔区域的周边部分，使得接触区域的上表面保持暴露。 然后去除接触区域内的电介质层的部分以形成从间隔物结构的上表面延伸到第一导电层的上表面的通孔（128）。 优选地，基本上小于光刻曝光设备的最小特征尺寸，间隔区域（110）的横向尺寸近似等于通孔（120）的横向尺寸中的光刻曝光设备的最小特征尺寸。