公开(公告)号：WO1998012839A1

公开(公告)日：1998-03-26

申请号：PCT/US1997003576

申请日：1997-03-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KALKUNTE, Mohan ,  KADAMBI, Jayant ,  MANGIN, James, Lawrence

IPC: H04L12/413

CPC classification number: H04L12/413

Abstract: A network includes a combination of carrier-sense stations and Universal Multiple Access (UMA) stations using a time slot multiple access protocol. The network is configured to include assigned time slots for the respective UMA stations and unassigned time slots reserved for the carrier-sense stations to access the shared network media. Each of the UMA stations is provided with a corresponding assigned time slot and the total number of time slots. Since the UMA stations access the media only during the assigned time slot, the carrier-sense stations can contend for access to the media after waiting a minimum interpacket gap (IPG) after sensing deassertion of the receive carrier on the media. The UMA stations may also be modified to attempt access of the media using Ethernet-compliant, carrier-sense multiple-access with collision detection (CSMA/CD) protocol when a current time slot corresponds to a mixed-use time slot.

Abstract translation: 网络包括使用时隙多址协议的载波侦听站和通用多路访问（UMA）站的组合。 网络被配置为包括用于相应UMA站的分配的时隙和为载波侦听站保留以访问共享网络媒体的未分配时隙。 每个UMA站都设有相应的分配时隙和总时隙数。 由于UMA站仅在分配的时隙期间才能访问媒体，因此在感知到媒体上的接收载波的取消消息之后等待最小分组间隙（IPG）后，载波侦听站可以争取接入媒体。 当当前时隙对应于混合使用时隙时，也可以修改UMA站以尝试使用具有冲突检测（CSMA / CD）协议的以太网兼容载波侦听多路访问的媒体访问。

公开(公告)号：WO1998011696A1

公开(公告)日：1998-03-19

申请号：PCT/US1997006888

申请日：1997-04-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  RUNALDUE, Thomas, Jefferson ,  KADAMBI, Jayant

IPC: H04L12/44

CPC classification number: H04L49/351

Abstract: The present invention comprises a system and method for reducing the pin count between a plurality of MAC and PHY devices within a switching element. In this embodiment, the switching element includes a plurality of general serial interfaces for providing connections between respective MAC and PHY devices and each of the plurality of general serial interfaces operates at a first data rate. The system and method comprises a multiplexer coupled to the plurality of general serial interfaces and a pad member including a plurality of pins. The pad member is coupled to the multiplexer and receives multiplexed signals from the plurality of general serial interfaces. The multiplexer operates at a second data rate that is a multiple of the first data rate. Generally, a system and method in accordance with the present invention allows for the multiplexing of a general purpose serial interface (GPSI) to reduce the pin count in some cases by as much as 75 % and also synchronize the MAC/PHY interface. In this example, the multiplexer interface uses a total of 7 pins and supports a total of four MAC/PHY connections. If only GPSIs were utilized, 28 pins would be required for this function. The same multiplexing technique will also reduce the MAC/PHY interface in four 100Mbps connections from 56 pins for a four port system to 18 pins. In each example the multiplexer interface will operate at four times the speed of the general serial interface.

Abstract translation: 本发明包括用于减少开关元件内的多个MAC和PHY器件之间的引脚计数的系统和方法。 在该实施例中，开关元件包括多个通用串行接口，用于提供相应MAC和PHY设备之间的连接，并且多个通用串行接口中的每一个以第一数据速率工作。 该系统和方法包括耦合到多个通用串行接口的多路复用器和包括多个引脚的焊盘构件。 焊盘构件耦合到多路复用器，并从多个通用串行接口接收复用的信号。 多路复用器以第一数据速率的倍数的第二数据速率操作。 通常，根据本发明的系统和方法允许多路复用通用串行接口（GPSI），以在一些情况下减少引脚数量高达75％，并且还使MAC / PHY接口同步。 在这个例子中，多路复用器接口共使用7个引脚，并且总共支持4个MAC / PHY连接。 如果仅使用GPSI，则此功能将需要28个引脚。 相同的复用技术还将减少四个100Mbps连接中的MAC / PHY接口，从56个引脚到四个端口系统到18个引脚。 在每个示例中，多路复用器接口将以通用串行接口的四倍速度运行。

公开(公告)号：WO1997048209A1

公开(公告)日：1997-12-18

申请号：PCT/US1997000858

申请日：1997-01-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KALKUNTE, Mohan ,  KADAMBI, Jayant ,  MANGIN, James, Laurance ,  KRISHNA, Gopal

IPC: H04L12/413

CPC classification number: H04L12/40163 ,  H04L12/40013 ,  H04L12/40136 ,  H04L12/413

Abstract: Delay times are modified in Ethernet network devices by adding an integer multiple of a delay interval to the minimum interpacket gap (IPG) interval, and decrementing the integer in each network station in response to detected activity on the media. Each station has a unique integer value from the range of zero to the number of stations (N) minus one. The unique integer value ensures that each station has a different delay interval in accessing the media after sensing deassertion of the receive carrier. The station having a zero integer value will have its integer counter reset to (N-1) after a station transmits a data packet on the network, and the stations having nonzero integer values decrement their respective integer counters. Each network station also includes a deferral timer that counts the maximum delay interval of (N-1) delay intervals plus the minimum IPG value, and thus establishes a bounded access latency for a half-duplex shared network.

Abstract translation: 通过将延迟间隔的整数倍添加到最小分组间隙（IPG）间隔，在以太网网络设备中修改延迟时间，并且响应于媒体上检测到的活动而递减每个网络站中的整数。 每个站具有从零到站数（N）减一的唯一整数值​​。 唯一的整数值确保每个站在感测到接收载波的取消消息之后在访问媒体时具有不同的延迟时间间隔。 在站点在网络上发送数据包之后，具有零整数值的站将其整数计数器重置为（N-1），并且具有非零整数值的站减少它们各自的整数计数器。 每个网络站还包括延迟定时器，其计数（N-1）个延迟间隔的最大延迟间隔加上最小IPG值，从而建立半双工共享网络的有界访问等待时间。

公开(公告)号：WO1997045985A1

公开(公告)日：1997-12-04

申请号：PCT/US1997001333

申请日：1997-01-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KADAMBI, Jayant ,  KALKUNTE, Mohan ,  MANGIN, James

IPC: H04L12/413

CPC classification number: H04L12/413

Abstract: Efficient communication in a network having a minimum data transmission time interval wherein a data packet is transmitted beginning at a start (t20) of the minimum data transmission time interval. An end (t26) of the minimum data transmission time interval is determined and then at least one next data packet is transmitted after the data packet if the end of the minimum data transmission time (t26) is after the end of the data packet (t21).

Abstract translation: 在具有最小数据传输时间间隔的网络中的有效通信，其中从最小数据传输时间间隔的开始（t20）开始发送数据分组。 确定最小数据传输时间间隔的结束（t26），并且如果最小数据传输时间（t26）的结束是在数据分组结束之后（t21），则在数据分组之后发送至少一个下一个数据分组 ）。

公开(公告)号：WO1998009408A1

公开(公告)日：1998-03-05

申请号：PCT/US1997006868

申请日：1997-04-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MANGIN, James, Lawrence ,  KADAMBI, Jayant ,  KALKUNTE, Mohan

IPC: H04L12/56

CPC classification number: H04L47/10 ,  H04L47/13 ,  H04L47/263 ,  H04L47/283 ,  H04L49/351

Abstract: Delay times are modified in full-duplex Ethernet network devices by calculating in each network station a delay interval based on a size of a transmitted data packet and a desired transmission rate. The network station waits the calculated delay time before transmitting another data packet, ensuring that the overall output transmission rate of the network station corresponds to the assigned desired transmission rate. The desired transmission rate is received as a media access control (MAC) control frame from a network management entity, such as a switched hub. Hence, each station operates at the desired transmission rate, minimizing the occurrence of congestion and eliminating the necessity of PAUSE frames.

Abstract translation: 在全双工以太网网络设备中通过在每个网络站中计算基于所发送的数据分组的大小和期望的传输速率的延迟间隔来修改延迟时间。 在发送另一个数据包之前，网络站等待所计算的延迟时间，确保网络站的总输出传输速率对应于所分配的所需传输速率。 从诸如交换式集线器的网络管理实体接收期望的传输速率作为媒体访问控制（MAC）控制帧。 因此，每个站以期望的传输速率操作，使拥塞的发生最小化并且消除了暂停帧的必要性。

公开(公告)号：WO1998006202A1

公开(公告)日：1998-02-12

申请号：PCT/US1997003417

申请日：1997-03-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KALKUNTE, Mohan ,  KADAMBI, Jayant ,  MANGIN, James, Lawrence ,  MERCHANT, Shashank, Chandravadan

IPC: H04L12/413

CPC classification number: H04L12/40156 ,  H04L12/413 ,  H04L12/6418 ,  H04L2012/6435 ,  H04L2012/6448 ,  H04L2012/6454 ,  H04L2012/6464

Abstract: Collision delay intervals are modified in Ethernet network devices transmitting priority data requiring a guaranteed latency by multiplying an integer multiple number of slot times with a fractional coefficient (92). A network device having priority data for transmission uses the conventional Truncated Binary Exponential Backoff (TREB) algorithm during the first access attempt to calculate a collision delay interval from a randomly selected integer multiple of slot times (88). If the network device encounters another collision (102), the next randomly selected integer multiple of slot times is multiplied by the fractional coefficient (92). Use of the fractional coefficient during collision mediation on a half-duplex Ethernet provides a bounded access latency for real-time and multimedia applications by granting the network device a higher probability of successfully accessing the network media.

Abstract translation: 在以太网网络设备中，通过将整数倍数的时隙乘以分数系数（92）来传送需要保证等待时间的优先级数据，在以太网网络设备中修改冲突延迟时间间隔。 具有传输优先权数据的网络设备在第一次接入尝试期间使用传统的截断二进制指数退避（TREB）算法来计算随机选择的时隙倍数（88）的冲突延迟间隔。 如果网络设备遇到另一个冲突（102），则将时隙时间的下一个随机选择的整数倍乘以分数系数（92）。 在半双工以太网以太网以太网交换机之间的冲突中介中使用分数系数通过授予网络设备成功访问网络媒体的可能性更高，为实时和多媒体应用提供有限的访问延迟。

公开(公告)号：EP0925670B1

公开(公告)日：2004-11-10

申请号：EP97924515.6

申请日：1997-04-22

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： RUNALDUE, Thomas, Jefferson ,  KADAMBI, Jayant

IPC: H04L12/44 ,  H04L29/08

CPC classification number: H04L49/351

Abstract: The present invention comprises a system and method for reducing the pin count between a plurality of MAC and PHY devices within a switching element. In this embodiment, the switching element includes a plurality of general serial interfaces for providing connections between respective MAC and PHY devices and each of the plurality of general serial interfaces operates at a first data rate. The system and method comprises a multiplexer coupled to the plurality of general serial interfaces and a pad member including a plurality of pins. The pad member is coupled to the multiplexer and receives multiplexed signals from the plurality of general serial interfaces. The multiplexer operates at a second data rate that is a multiple of the first data rate. Generally, a system and method in accordance with the present invention allows for the multiplexing of a general purpose serial interface (GPSI) to reduce the pin count in some cases by as much as 75 % and also synchronize the MAC/PHY interface. In this example, the multiplexer interface uses a total of 7 pins and supports a total of four MAC/PHY connections. If only GPSIs were utilized, 28 pins would be required for this function. The same multiplexing technique will also reduce the MAC/PHY interface in four 100Mbps connections from 56 pins for a four port system to 18 pins. In each example the multiplexer interface will operate at four times the speed of the general serial interface.

公开(公告)号：EP0904645A1

公开(公告)日：1999-03-31

申请号：EP97903014.0

申请日：1997-01-21

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： KALKUNTE, Mohan ,  KADAMBI, Jayant ,  MANGIN, James, Laurance ,  KRISHNA, Gopal

IPC: H04L12

CPC classification number: H04L12/40163 ,  H04L12/40013 ,  H04L12/40136 ,  H04L12/413

Abstract: Delay times are modified in Ethernet network devices by adding an integer multiple of a delay interval to the minimum interpacket gap (IPG) interval, and decrementing the integer in each network station in response to detected activity on the media. Each station has a unique integer value from the range of zero to the number of stations (N) minus one. The unique integer value ensures that each station has a different delay interval in accessing the media after sensing deassertion of the receive carrier. The station having a zero integer value will have its integer counter reset to (N-1) after a station transmits a data packet on the network, and the stations having nonzero integer values decrement their respective integer counters. Each network station also includes a deferral timer that counts the maximum delay interval of (N-1) delay intervals plus the minimum IPG value, and thus establishes a bounded access latency for a half-duplex shared network.

公开(公告)号：EP0927474B1

公开(公告)日：2003-05-21

申请号：EP97914900.2

申请日：1997-03-07

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： KALKUNTE, Mohan ,  KADAMBI, Jayant ,  MANGIN, James, Lawrence

IPC: H04L12/413 ,  H04L12/64

CPC classification number: H04L12/413

Abstract: A network includes a combination of carrier-sense stations and Universal Multiple Access (UMA) stations using a time slot multiple access protocol. The network is configured to include assigned time slots for the respective UMA stations and unassigned time slots reserved for the carrier-sense stations to access the shared network media. Each of the UMA stations is provided with a corresponding assigned time slot and the total number of time slots. Since the UMA stations access the media only during the assigned time slot, the carrier-sense stations can contend for access to the media after waiting a minimum interpacket gap (IPG) after sensing deassertion of the receive carrier on the media. The UMA stations may also be modified to attempt access of the media using Ethernet-compliant, carrier-sense multiple-access with collision detection (CSMA/CD) protocol when a current time slot corresponds to a mixed-use time slot.

公开(公告)号：EP0925670A1

公开(公告)日：1999-06-30

申请号：EP97924515.0

申请日：1997-04-22

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： RUNALDUE, Thomas, Jefferson ,  KADAMBI, Jayant

IPC: H04L12

CPC classification number: H04L49/351

Abstract: The present invention comprises a system and method for reducing the pin count between a plurality of MAC and PHY devices within a switching element. In this embodiment, the switching element includes a plurality of general serial interfaces for providing connections between respective MAC and PHY devices and each of the plurality of general serial interfaces operates at a first data rate. The system and method comprises a multiplexer coupled to the plurality of general serial interfaces and a pad member including a plurality of pins. The pad member is coupled to the multiplexer and receives multiplexed signals from the plurality of general serial interfaces. The multiplexer operates at a second data rate that is a multiple of the first data rate. Generally, a system and method in accordance with the present invention allows for the multiplexing of a general purpose serial interface (GPSI) to reduce the pin count in some cases by as much as 75 % and also synchronize the MAC/PHY interface. In this example, the multiplexer interface uses a total of 7 pins and supports a total of four MAC/PHY connections. If only GPSIs were utilized, 28 pins would be required for this function. The same multiplexing technique will also reduce the MAC/PHY interface in four 100Mbps connections from 56 pins for a four port system to 18 pins. In each example the multiplexer interface will operate at four times the speed of the general serial interface.