公开(公告)号：JPS6420756A

公开(公告)日：1989-01-24

申请号：JP17595187

申请日：1987-07-16

Applicant: FUJITSU LTD

Inventor： HASEBE TAKAYUKI ,  NOJIMA SATOSHI ,  TSUTSUI HIDEKAZU ,  KANOUCHI JUNICHI ,  TOMINAGA SUSUMU

IPC: H04L12/711

Abstract: PURPOSE:To decrease the missing of a packet in a network due to the occurrence of a fault and to reduce communication interruption time by turning a call through a reverse path if a fault is detected in a forward path and detouring it through the detour route. CONSTITUTION:In connecting a call to a terminal 2 from the start of call form a terminal 1, for example, a route 1 in forward direction through packet exchanges 3, 4, 5, 6 is set at call setting and a detour-route II through the packet exchanges 3, 7, 8, 6 is set. If a fault takes place in the packet exchange 5 in the forward path I, the fault is detected by a pre-stage packet exchange 4 and it is informed to the packet exchange 3. Thus, the packet exchange 3 detours the call from the terminal 1 from the forward route I to the detour route II to connect it to the terminal 2. Thus, the intermission time of the communication due to the fault is reduced remarkably and the missing packet due to the fault is reduced.

公开(公告)号：JPS63226151A

公开(公告)日：1988-09-20

申请号：JP12843987

申请日：1987-05-27

Applicant: FUJITSU LTD

Inventor： TOMINAGA SUSUMU ,  NOJIMA SATOSHI ,  TSUTSUI HIDEKAZU ,  KANOUCHI JUNICHI ,  FUKUDA HARUKI

IPC: H04L29/06

Abstract: PURPOSE:To improve transmission efficiency by providing a packet memory corresponding to each of the priority given to each packet, on both a transmission system and a reception system. CONSTITUTION:When a second packet whose priority is high is inputted from an input signal line 11, and written to a memory 110-n, a transmission system 100 suspends the transmission of a first packet, and starts the transmission of a second packet. In this case, a flag adding circuit 120 adds a packet delimiting flag to the second packet and sends it out to a transmission line 30. A reception system 200 detects its flag by a flag detecting circuit 220, suspends write and read-out to and from the memory 210-1 of the first packet which is receiving, and writes the second packet to a memory 210-n. Also, it is read out and sent out to an output signal line 22. Subsequently, the remaining part of the first packet which has been suspended is read out of the corresponding memory 110-1, and its transmission is started continuously after the regular flag of a termination of the second packet. In such a way, the transmission efficiency can be improved.

公开(公告)号：JPS63106856A

公开(公告)日：1988-05-11

申请号：JP25288486

申请日：1986-10-24

Applicant: FUJITSU LTD

Inventor： SAKAKAWA KAZUO ,  NOJIMA SATOSHI ,  FUKUDA HARUKI

IPC: G06F13/12

Abstract: PURPOSE:To suppress the influence of a propagation delay time at a low level, by adding a power source state storing and monitoring means which stores and monitors the ON/OFF state of a power source sent from a first frame transmission/reception part to a first distance extending device. CONSTITUTION:On the first distance extending device, the power source state storing and monitoring means 22 which stores the ON/OFF state of the power source of an input/output device, that is, whether it is possible to be used or not, is provided. In other words, since it is that the response of an OPi can be obtained when the input/output device can be used for an ADRo and a SELo from an input/output channel device at time of initial sequence, an OPi-ON is sent to the input/output channel device from the first distance extending device by performing the preceding control of the OPi if it is recognized that the input/output device can be used in the first distance extending device. In this way, it is possible to accelerate the timing of the sending of an ADRo-OFF from the input/output channel device, and also, to reduce the influence of the propagation delay time.

公开(公告)号：JPS6376040A

公开(公告)日：1988-04-06

申请号：JP22235386

申请日：1986-09-19

Applicant: FUJITSU LTD

Inventor： NOJIMA SATOSHI ,  FUKUDA HARUKI ,  TSUTSUI HIDEKAZU

IPC: G06F13/12 ,  G06F13/36

Abstract: PURPOSE:To contrive to reduce a useless transmission time and a processing time by controlling a switching part by stored information so that the succeeding signals, data, etc., are transmitted/received to/from an I/O unit included in a selected control unit and other nodes are by-passed. CONSTITUTION:Nodes S3-1-3-n detect whether slave control units are selected or not and store the detected results in storage devices 30-1-30n respectively. Switching parts 31-1-31-n in the nodes S3-1-3-n are controlled by the stored information and only the node S whose slave control unit is selected transmits a signal, etc., obtained from a channel device 1 to the selected slave control unit or transmits a signal, data, etc., from the control unit to the channel device 1. On the other hand, unselected nodes S by-pass the transmission of the succeeding signal, data and so on. Thus, the useless transmission time and processing time can be reduced.

公开(公告)号：JPS62219732A

公开(公告)日：1987-09-28

申请号：JP6151086

申请日：1986-03-19

Applicant: FUJITSU LTD

Inventor： TSUTSUI HIDEKAZU ,  NOJIMA SATOSHI ,  HASHIMOTO MASAMICHI ,  KANOCHI JUNICHI ,  SAKAKAWA KAZUO

Abstract: PURPOSE:To improve the utilizing efficiency by providing a packet reconstituting means using a multiplexing FIFO so as to multiplex and send a packet when a flag representing the possibility of multiplexing is set in the inputted packet and sending the packet as it is when the flag representing disabled multiplexing is set. CONSTITUTION:When the packet exists in the 2nd FIFO memory, it is absorbed and inputted to a multiplexing flag eliminating section 42 in a transmission line sending section. When a certain degree of unit packets are stored in a multiplex packet assembling FIFO memory 44 in a transmission line adaptor section 47, a switch 46 is outputted to the position (c) to output the content of the multiplex packet assembling FIFO memory 44 and they are sent to the transmission line as a multiplex packet. In other cases, the switch 46 is switched to the position (d) and the content of a single packet storage FIFO memory 45 is sent to the transmission line as a unit packet. Further, in sending a packet in the transmission line adaptor section 47, a frame check sequence FCS and a flag F are added to the packet and the result is sent to the transmission line. Thus, the transmission efficiency is improved.

公开(公告)号：JPS62104340A

公开(公告)日：1987-05-14

申请号：JP24442385

申请日：1985-10-31

Applicant: FUJITSU LTD

Inventor： TSUTSUI HIDEKAZU ,  KAZETANI KIYOSHI ,  NOJIMA SATOSHI

Abstract: PURPOSE:To simplify connection constitution and control, and to speed up the operation of a packet exchange and accelerate an increase in capacity by providing each transmission line with a connection path only at a switching unit and connecting the transmission line to a controller through the switching unit. CONSTITUTION:Logical channels set for respective transmission lines 1 are classified by a logical channel LCc 1 for control which transmits a control packet Pc and a logical channel LCd for data which transmits data packet Pd, and given a logical channel number LCNc 1 for control and a logical channel number LCNd for data. A connection path 6 provided between the transmission line and controller 5 is provided with only a logical channel LCc 2 for control and given a logical channel number LCNc 2 for control. A control panel Pc or data packet Pd is transferred to the logical channel LCc 1 or LCd on the transmission line 1 and a control packet Pc is transferred to the logical channel LCc 2 on the connection path 6 similarly.

公开(公告)号：JPS62103729A

公开(公告)日：1987-05-14

申请号：JP24316285

申请日：1985-10-30

Applicant: FUJITSU LTD

Inventor： TOMINAGA SUSUMU ,  TSUTSUI HIDEKAZU ,  NOJIMA SATOSHI

IPC: G11C7/00 ,  G06F5/06 ,  G06F5/10 ,  G06F5/12

Abstract: PURPOSE:To prevent defective data from being generated by storing and extracting a section signal which indicates the section of data groups together with data and signifying a reset signal after the storage or extraction of the section signal. CONSTITUTION:The section signal (g) which indicates the section of data groups consisting of plural succeeding data (d) is stored and extracted together with the data (d) and an initialization control means 100 is provided which signifies the reset signal (r) after the input or output of the section signal (g) when a reset signal (r) which initializes the data (d) being stored from outside is received while the section signal (g) is inputted from a precedent circuit or while the section signal (g) is outputted to a trailing circuit. Consequently, even when the reset signal is inputted, defective data in which part of the data groups is absent is prevented from being transmitted to the trailing circuit.

公开(公告)号：JPS61224754A

公开(公告)日：1986-10-06

申请号：JP6562585

申请日：1985-03-29

Applicant: FUJITSU LTD

Inventor： NOJIMA SATOSHI ,  HASHIMOTO MASAMICHI ,  KANOCHI JUNICHI ,  TSUTSUI HIDEKAZU

Abstract: PURPOSE:To obtain a throughput with high efficiency and high accuracy by measuring the packet propagation time reflected with the resource utilizing state and deciding the timing of packet transmission depending on the turn-around time. CONSTITUTION:A sending station receiving a request of transmission sends a packet described with a sending time T1 to the next relay station via an OR circuit 13. The reception station side receives the said frame, a time stamp read circuit 18 reads it, outputs the result to a response frame forming circuit 17 to form a response frame, which is sent to the sending station via the OR circuit 13. The sending station receives the said response frame, the time stamp read circuit 18 reads a time stamp and inputs an inter-network propagation time Tpd to a calculation circuit 15. The calculation circuit 15 reads the present time T2 from a clock 16 to calculate Tpd (T2-T1)/2. A Tpd waiting time circuit 14 receives the Tpd from the calculation circuit 15 and the value is used as the inter-network propagation time of a new packet.

公开(公告)号：JPS61133743A

公开(公告)日：1986-06-21

申请号：JP25593484

申请日：1984-12-04

Applicant: Fujitsu Ltd

Inventor： TSUTSUI HIDEKAZU ,  NOJIMA SATOSHI

IPC: H04L13/08

Abstract: PURPOSE: To attain packet flow control by using an input terminal of an FIFO memory as a packet queue for both read/write to read the data storage quantity of the FIFO memory at reading.
CONSTITUTION: When an input transfer circuit TU3 reads, e.g., a byte number in the FIFO memory 7a, an READ/WRITE signal line 20 is operated to throw a changeover switch 16 to the position (a). Thus, an output of a subtractor 12 appears on an input data signal line 21. The TU3 reads the value and when it is discriminated that the packet is stored in the FIFO memory 7a, the changeover switch 16 is thrown to the position (b) to input the packet data to a RAM13 together with a shift-insignal. The shift-in signal is generated synchronously with the input timing signal. On the other hand, packet transmission sections 8a∼8c checks an EMPTY signal to detect that the packet counter 14 is not 0 and transmits the packet data to corresponding output signal paths 9a∼9c together with a shift-out signal.
COPYRIGHT: (C)1986,JPO&Japio

Abstract translation: 目的：通过使用FIFO存储器的输入端作为读/写的分组队列来获取分组流控制，以读取FIFO存储器的数据存储量。 构成：当输入传送电路TU3读取例如FIFO存储器7a中的字节数时，操作READ / WRITE信号线20将切换开关16投入到位置（a）。 因此，减法器12的输出出现在输入数据信号线21上.TU3读取该值，并且当识别出分组被存储在FIFO存储器7a中时，转换开关16被抛出到位置（b） 将分组数据与移位信息一起输入到RAM13。 移位信号与输入定时信号同步产生。 另一方面，分组发送部分8a-8c检查EMPTY信号以检测分组计数器14不是0，并且将分组数据与偏移信号一起发送到对应的输出信号路径9a-9c。

公开(公告)号：JPS60192445A

公开(公告)日：1985-09-30

申请号：JP4834484

申请日：1984-03-14

Applicant: Fujitsu Ltd

Inventor： MATSUDA MASAHIRO ,  TAKEYAMA AKIRA ,  TAZAKI TAKASHI ,  NOJIMA SATOSHI ,  AZUMA MITSUHIRO

IPC: H04L12/26

CPC classification number: H04L12/43

Abstract: PURPOSE:To prevent a data circulated through a transmission line after being transmitted from the own node from being fetched at the own node again by processing a confirming bit and transmitting the processed result to a loop form transmission line when the own node use or release the time slot designated by a highway supervisory device. CONSTITUTION:When the use of a time slot and the data transmission between nodes ND1 and ND2 counter clockwise as shown in the figure are informed from a highway supervisory control section SV, since the SV does not exist in the node ND1 up to the node ND2, it is assigned in advance in the ND1 that the data of the time slot TS1 is a normal communication data when the 2nd bit of a communication enable/disable confirming bit BHD is logical 1. In transmitting a data from the node ND2 to the ND1, since the SV exists, it is assigned in advance that the data of the time slot TS1 is normal when the said bit goes to ''0''. Thus, the node ND1 brings the level of the 2nd bit of the BHD to ''1'', and the data is superimposed on the time slot and transmitted toward the ND2.

Abstract translation: 目的：为了防止在通过传输自己的节点传送的数据在通过处理确认位再次通过处理确认位并将处理的结果发送到环形传输线时，在自身节点上传送的数据被传送到自身节点，当自身节点使用或释放 由公路监控设备指定的时隙。 构成：从公路监控部SV通知使用时隙和节点ND1和ND2之间的数据传输如图所示，由于SV不存在节点ND1直到节点ND2 ，在通信使能/禁止确认位BHD的第2位为逻辑1的情况下，在ND1中预先分配时隙TS1的数据为正常通信数据。在将数据从节点ND2发送到ND1时 由于SV存在，因此当所述位变为“0”时，预先分配时隙TS1的数据正常。 因此，节点ND1使BHD的第2位的电平为“1”，数据叠加在时隙上并向ND2发送。