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公开(公告)号:MX2015009458A
公开(公告)日:2015-09-24
申请号:MX2015009458
申请日:2013-12-06
Applicant: IBM
Inventor: SLEGEL TIMOTHY , SCHWARZ ERIC MARK , BRADBURY JONATHAN DAVID , GSCHWIND MICHAEL KARL
IPC: G06F17/16
Abstract: Se facilita el manejo de la excepción del vector. Se ejecuta una instrucción vectorial que opera en uno o más elementos de un registro del vector. Cuando una excepción se encuentra durante la ejecución de la instrucción, se proporciona un código de excepción del vector, que indica una posición dentro del registro del vector que causó la excepción. El código de excepción del vector también incluye una razón para la excepción.
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公开(公告)号:AU2013375139A1
公开(公告)日:2015-07-16
申请号:AU2013375139
申请日:2013-12-04
Applicant: IBM
Inventor: BRADBURY JONATHAN DAVID , SCHWARZ ERIC MARK
IPC: G06F9/30
Abstract: A Vector Checksum instruction. Elements from a second operand are added together one- by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.
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93.
公开(公告)号:GB2513797A
公开(公告)日:2014-11-05
申请号:GB201415054
申请日:2013-03-01
Applicant: IBM
Inventor: BRADBURY JONATHAN DAVID , GSCHWIND MICHAEL KARL , SLEGEL TIMOTHY
Abstract: Copying characters of a set of terminated character data from one memory location to another memory location using parallel processing and without causing unwarranted exceptions. The character data to be copied is loaded within one or more vector registers. In particular, in one embodiment, an instruction (e.g., a Vector Load to block Boundary instruction) is used that loads data in parallel in a vector register to a specified boundary, and provides a way to determine the number of characters loaded. To determine the number of characters loaded (a count), another instruction (e.g., a Load Count to Block Boundary instruction) is used. Further, an instruction (e.g., a Vector Find Element Not Equal instruction) is used to find the index of the first delimiter character, i.e., the first termination character, such as a zero or null character within the character data. This instruction checks a plurality of bytes of data in parallel.
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公开(公告)号:SG11201404862RA
公开(公告)日:2014-09-26
申请号:SG11201404862R
申请日:2013-03-07
Applicant: IBM
Inventor: BRADBURY JONATHAN DAVID , SCHWARZ ERIC MARK , SLEGEL TIMOTHY , GSCHWIND MICHAEL KARL
Abstract: Processing of character data is facilitated. A Find Element Not Equal instruction is provided that compares data of multiple vectors for inequality and provides an indication of inequality, if inequality exists. An index associated with the unequal element is stored in a target vector register. Further, the same instruction, the Find Element Not Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare.
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公开(公告)号:AU2013233974A1
公开(公告)日:2014-09-11
申请号:AU2013233974
申请日:2013-03-01
Applicant: IBM
Inventor: BRADBURY JONATHAN DAVID , GSCHWIND MICHAEL KARL , SLEGEL TIMOTHY
IPC: H03M7/40
Abstract: The length of character data having a termination character is determined. The character data for which the length is to be determined is loaded, in parallel, within one or more vector registers. An instruction is used that loads data in a vector register to a specified boundary, and provides a way to determine the number of characters loaded, using, for instance, another instruction. Further, an instruction is used to find the index of the first termination character, e.g., the first zero or null character. This instruction searches the data in parallel for the termination character. By using these instructions, the length of the character data is determined using only one branch instruction.
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公开(公告)号:AU2012373736A1
公开(公告)日:2014-09-11
申请号:AU2012373736
申请日:2012-11-15
Applicant: IBM
Inventor: BRADBURY JONATHAN DAVID , GSCHWIND MICHAEL KARL , SCHWARZ ERIC MARK , SLEGEL TIMOTHY , JACOBI CHRISTIAN
IPC: G11C11/00
Abstract: A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined.
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公开(公告)号:AU2012373734A1
公开(公告)日:2014-09-11
申请号:AU2012373734
申请日:2012-11-15
Applicant: IBM
Inventor: BRADBURY JONATHAN DAVID , GSCHWIND MICHAEL KARL , SLEGEL TIMOTHY , SCHWARZ ERIC MARK , JACOBI CHRISTIAN
IPC: G06F12/10
Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.
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98.
公开(公告)号:MX383434B
公开(公告)日:2025-03-14
申请号:MX2016012532
申请日:2016-09-26
Applicant: IBM
Inventor: GAINEY CHARLES , JACOBI CHRISTIAN , BUSABA FADI YUSUF , GREINER DAN , KUBALA JEFFREY PAUL , BRADBURY JONATHAN DAVID , HELLER LISA CRANTON , FARRELL MARK , OSISEK DAMIAN LEO , SCHMIDT DONALD WILLIAM , SLEGEL TIMOTHY
Abstract: Las modalidades se refieren a subprocesamiento múltiple en una computadora. Un aspecto es una computadora que incluye una configuración que tiene un núcleo que incluye subprocesos físicos y es operable en modos de subprocesamiento individual (ST) y subprocesamiento múltiple (MT). La computadora también incluye un programa anfitrión configurado para ejecutarse en el modo ST en el núcleo para emitir una instrucción de inicio de ejecución virtual (inicio de VE) para distribuir una entidad invitada que incluye una máquina virtual (VM) invitada. La instrucción de inicio de VE se ejecuta por el núcleo e incluye obtener una descripción de estado, que tiene un estado de invitado, desde una ubicación especificada por la instrucción de inicio de VE. La ejecución incluye determinar, con base en el estado de invitado, si la entidad invitada incluye un subproceso invitado individual o múltiples subprocesos invitados, e iniciar los subprocesos invitados en el modo MT o modo ST con base en el estado de invitado y una determinación de si la entidad invitada incluye un subproceso invitado individual o múltiples subprocesos invitados.
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公开(公告)号:CA2940988C
公开(公告)日:2022-08-16
申请号:CA2940988
申请日:2015-03-16
Applicant: IBM
Inventor: GREINER DAN , FARRELL MARK , OSISEK DAMIAN LEO , SCHMIDT DONALD WILLIAM , BUSABA FADI YUSUF , KUBALA JEFFREY PAUL , BRADBURY JONATHAN DAVID , HELLER LISA CRANTON , SLEGEL TIMOTHY , GAINEY CHARLES
IPC: G06F9/46
Abstract: THREAD CONTEXT RESTORATION IN A MULTITHREADING COMPUTER SYSTEM Amultithreading computer system includesa configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method including disabling one or more secondary threads based on switching from MT mode to ST mode. A thread context of secondary threads is made unavailable to programs. Based on a last-set program-specified maximum thread-id indicating MT, the thread context is obtained by a) executing a set MT instruction to resume the MT mode, and b) based on being in the resumed MT mode, accessing the thread context.
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公开(公告)号:AU2015357677B2
公开(公告)日:2018-11-08
申请号:AU2015357677
申请日:2015-10-30
Applicant: IBM
Inventor: BRADBURY JONATHAN DAVID , JACOBI CHRISTIAN , SLEGEL TIMOTHY , GSCHWIND MICHAEL KARL
Abstract: A method for accessing data in a memory coupled to a processor comprising: receiving a memory reference instruction for accessing data of a first size at an address in the memory; determining an alignment size of the address in the memory; and accessing the data of the first size in one or more groups of data by accessing each group of data block concurrently. The groups of data have sizes that are multiples of the alignment size.
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