公开(公告)号：CA2940990C

公开(公告)日：2022-08-23

申请号：CA2940990

申请日：2015-03-16

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY CHARLES

IPC: G06F9/46

Abstract: A computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method that includes accessing the primary thread in the ST mode using a core address value and switching from the ST mode to the MT mode. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value, where the expanded address value includes the core address value concatenated with a thread address value.

公开(公告)号：AU2015238665B2

公开(公告)日：2018-01-18

申请号：AU2015238665

申请日：2015-03-16

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY JR CHARLES

IPC: G06F9/50 ,  G06F9/38

Abstract: A computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method that includes accessing the primary thread in the ST mode using a core address value and switching from the ST mode to the MT mode. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value, where the expanded address value includes the core address value concatenated with a thread address value.

公开(公告)号：SG11201606093QA

公开(公告)日：2016-08-30

申请号：SG11201606093Q

申请日：2015-03-16

Applicant: IBM

Inventor： HELLER LISA CRANTON ,  BRADBURY JONATHAN DAVID ,  KUBALA JEFFREY PAUL ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  GREINER DAN ,  SLEGEL TIMOTHY ,  BUSABA FADI YUSUF ,  SCHMIDT DONALD WILLIAM

IPC: G06F9/455 ,  G06F9/50

公开(公告)号：SG11201606089QA

公开(公告)日：2016-08-30

申请号：SG11201606089Q

申请日：2015-03-16

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY

IPC: G06F9/50 ,  G06F9/38

Abstract: Embodiments relate to address expansion and contraction in a multithreading computer system. According to one aspect, a computer implemented method for address adjustment in a configuration is provided. The configuration includes a core configurable between an ST mode and an MT mode, where the ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The primary thread is accessed in the ST mode using a core address value. Switching from the ST mode to the MT mode is performed. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value. The expanded address value includes the core address value concatenated with a thread address value.

公开(公告)号：MX338377B

公开(公告)日：2016-04-13

申请号：MX2014015291

申请日：2013-06-12

Applicant: IBM

Inventor： GREINER DAN ,  OSISEK DAMIAN LEO ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN

IPC: G06F11/36 ,  G06F9/46

Abstract: Una transacción es iniciada en un medio ambiente de cómputo y en base a la detección de un evento de registro de evento de programa, se presenta una instrucción para una transacción. Subsecuente a la interrupción, se establecen uno o más controles para inhibir la presentación de otra interrupción en base a la detección de otro evento de PER. Después de esto, la transacción es re-ejecutada y los eventos de PER detectados durante la ejecución de la transacción son ignorados.

公开(公告)号：CA2940905A1

公开(公告)日：2015-10-01

申请号：CA2940905

申请日：2015-03-19

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY CHARLES JR ,  JACOBI CHRISTIAN

IPC: G06F9/46 ,  G06F9/50

Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.

公开(公告)号：AU2010355814B2

公开(公告)日：2014-05-15

申请号：AU2010355814

申请日：2010-11-08

Applicant: IBM

Inventor： GREINER DAN ,  OSISEK DAMIAN LEO ,  SLEGEL TIMOTHY ,  HELLER LISA

IPC: G06F9/455 ,  G06F9/30

Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.

公开(公告)号：PL2430532T3

公开(公告)日：2014-04-30

申请号：PL10775820

申请日：2010-11-08

Applicant: IBM

Inventor： GREINER DAN ,  OSISEK DAMIAN LEO ,  SLEGEL TIMOTHY ,  HELLER LISA

IPC: G06F9/455 ,  G06F9/30

公开(公告)号：SI2430532T1

公开(公告)日：2014-02-28

申请号：SI201030428

申请日：2010-11-08

Applicant: IBM

Inventor： GREINER DAN ,  OSISEK DAMIAN LEO ,  SLEGEL TIMOTHY ,  HELLER LISA

IPC: G06F9/00

公开(公告)号：CA2800640A1

公开(公告)日：2011-12-29

申请号：CA2800640

申请日：2010-11-08

Applicant: IBM

Inventor： GREINER DAN ,  OSISEK DAMIAN LEO ,  SLEGEL TIMOTHY ,  HELLER LISA

IPC: G06F9/455 ,  G06F9/30

Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.