GEMEINSAME SPEICHERNUTZUNG ZWISCHEN EINER SICHEREN DOMÄNE UND EINER NICHT SICHEREN ENTITÄT

    公开(公告)号:DE112020000223T5

    公开(公告)日:2021-08-26

    申请号:DE112020000223

    申请日:2020-03-02

    Applicant: IBM

    Abstract: Gemäß einer oder mehreren Ausführungsformen der vorliegenden Erfindung umfasst ein durch einen Computer umgesetztes Verfahren ein Aktivieren, durch eine sichere Schnittstellensteuerung eines Computersystems, einer nicht sicheren Entität des Computersystems, um auf eine Seite eines Arbeitsspeichers, der zwischen der nicht sicheren Entität und einer sicheren Domäne des Computersystems gemeinsam genutzt wird, auf Grundlage der Seite zuzugreifen, die mit einem deaktivierten Indikator „Sicherer Speicherschutz“ der Seite als „Nicht sicher“ gekennzeichnet ist. Die sichere Schnittstellensteuerung kann überprüfen, dass der Indikator „Sicherer Speicherschutz“ der Seite deaktiviert ist, bevor der nicht sicheren Entität erlaubt wird, auf die Seite zuzugreifen. Die sichere Schnittstellensteuerung kann einer sicheren Entität der sicheren Domäne Zugriff auf die Seite ohne eine Überprüfung des Indikators „Sicherer Speicherschutz“ der Seite bereitstellen.

    DISPATCHING MULTIPLE THREADS IN A COMPUTER

    公开(公告)号:ZA201606254B

    公开(公告)日:2017-08-30

    申请号:ZA201606254

    申请日:2016-09-09

    Applicant: IBM

    Abstract: According to one aspect, a computer system includes a configuration with a machine enabled to operate in a single thread (ST) mode and a multithreading (MT) mode. In addition, the machine includes physical threads. The machine is configured to perform a method that includes issuing a start-virtual-execution (start-VE) instruction to dispatch a guest entity having multiple logical threads on the core. The guest entity includes all or a part of a guest virtual machine (VM), and issuing is performed by a host running on one of the physical threads on the core in the ST mode. The executing of the start-VE instruction by the machine includes mapping each of the logical threads to a corresponding one of the physical threads, initializing each of the mapped physical threads with a state of the corresponding logical thread, and starting execution of the guest entity on the core in MT mode.

    DYNAMIC ENABLEMENT OF MULTITHREADING

    公开(公告)号:CA2940905A1

    公开(公告)日:2015-10-01

    申请号:CA2940905

    申请日:2015-03-19

    Applicant: IBM

    Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.

    DYNAMIC ENABLEMENT OF MULTITHREADING

    公开(公告)号:CA2940905C

    公开(公告)日:2022-08-16

    申请号:CA2940905

    申请日:2015-03-19

    Applicant: IBM

    Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.

    SECURE STORAGE ISOLATION
    10.
    发明专利

    公开(公告)号:CA3132781A1

    公开(公告)日:2020-09-17

    申请号:CA3132781

    申请日:2020-03-02

    Applicant: IBM

    Abstract: An computer-implemented method according to examples includes receiving, by a secure interface control of a computing system, a request by a requestor to access a page in a memory of the computing system. The method further includes, responsive to determining that the requestor is a non-secure requestor and responsive to a secure- storage bit being set, prohibiting access to the page without performing an authorization check. The method further includes, responsive to determining that the requestor is a secure requestor, performing the authorization check.

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