公开(公告)号：US11093277B2

公开(公告)日：2021-08-17

申请号：US16913265

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US11030126B2

公开(公告)日：2021-06-08

申请号：US15650112

申请日：2017-07-14

Applicant: INTEL CORPORATION

Inventor： David A. Koufaty ,  Rajesh M. Sankaran ,  Stephen R. Van Doren

IPC: G06F3/06 ,  G06F13/16 ,  G06F15/78 ,  G06F9/46 ,  G06F21/71 ,  G06F12/10 ,  G06F21/79

Abstract: Techniques and apparatus to manage access to accelerator-attached memory are described. In one embodiment, an apparatus to provide coherence bias for accessing accelerator memory may include at least one processor, a logic device communicatively coupled to the at least one processor, a logic device memory communicatively coupled to the logic device, and logic, at least a portion comprised in hardware, the logic to receive a request to access the logic device memory from the logic device, determine a bias mode associated with the request, and provide the logic device with access to the logic device memory via a device bias pathway responsive to the bias mode being a device bias mode. Other embodiments are described and claimed.

公开(公告)号：US10970238B2

公开(公告)日：2021-04-06

申请号：US16566865

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  David J. Harriman ,  Sean O. Stalley ,  Rupin H. Vakharwala ,  Ishwar Agarwal ,  Pratik M. Marolia ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F13/42

Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

公开(公告)号：US10936490B2

公开(公告)日：2021-03-02

申请号：US15634785

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Edwin Verplanke ,  Stephen R. Van Doren ,  Ravishankar Iyer ,  Eric R. Wehage ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Jeffrey D. Chamberlain ,  Julius Mandelblat ,  Yen-Cheng Liu ,  Stephen T. Palermo ,  Tsung-Yuan C. Tai

IPC: G06F12/08 ,  G06F12/0811 ,  G06F13/42 ,  G06F9/455 ,  G06F9/50 ,  G06F12/1009 ,  G06F13/16

Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

公开(公告)号：US10789370B2

公开(公告)日：2020-09-29

申请号：US15470270

申请日：2017-03-27

Applicant: INTEL CORPORATION

Inventor： Mohan K. Nair ,  Rajesh M. Sankaran ,  Utkarsh Y. Kakaiya ,  Zhenfu Chai ,  David M. Lee ,  Pratik M. Marolia

IPC: G06F9/4401 ,  G06F21/60 ,  G06F21/85 ,  G06F21/57 ,  G06F12/0815 ,  G06F13/42 ,  H04L29/06

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for extending a root complex to encompass an external component. A processor includes a processor core and root complex circuitry coupled to the processor core. The processor core is to execute a basic input/output system (BIOS) and an operating system (OS). The root complex circuitry includes a coherent interface port and a downstream port. The root complex circuitry is to couple to an external component via the downstream port and the coherent interface port. The BIOS, to extend a root complex beyond the root complex circuitry to encompass the external component, is to obfuscate the downstream port from the OS, define a virtual root bridge for the external component, and enable a security check at the external component to provide protection for the coherent interface port and the downstream port.

公开(公告)号：US20200004703A1

公开(公告)日：2020-01-02

申请号：US16566865

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  David J. Harriman ,  Sean O. Stalley ,  Rupin H. Vakharwala ,  Ishwar Agarwal ,  Pratik M. Marolia ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F13/42

Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

公开(公告)号：US20180246827A1

公开(公告)日：2018-08-30

申请号：US15900771

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Rajesh M. Sankaran

IPC: G06F13/34

Abstract: Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

公开(公告)号：US09747208B2

公开(公告)日：2017-08-29

申请号：US15411658

申请日：2017-01-20

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Rajesh M. Sankaran ,  Subramanya R. Dulloor ,  Andrew V. Anderson

IPC: G06F13/00 ,  G06F12/0804 ,  G06F11/14

CPC classification number: G06F12/0804 ,  G06F9/467 ,  G06F11/07 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0793 ,  G06F11/14 ,  G06F11/1482 ,  G06F12/0868 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2212/1032 ,  G06F2212/608

Abstract: A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.

公开(公告)号：US20170242628A1

公开(公告)日：2017-08-24

申请号：US15589653

申请日：2017-05-08

Applicant: Intel Corporation

Inventor： Subramanya R. Dulloor ,  Rajesh M. Sankaran ,  Sanjay Kumar

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/214 ,  G06F2212/7201

Abstract: Hardware apparatuses and methods for distributed durable and atomic transactions in non-volatile memory are described. In one embodiment, a hardware apparatus includes a hardware processor, a plurality of hardware memory controllers for each of a plurality of non-volatile data storage devices, and a plurality of staging buffers with a staging buffer for each of the plurality of hardware memory controllers, wherein each of the plurality of hardware memory controllers are to: write data of a data set that is to be written to the plurality of non-volatile data storage devices to their staging buffer, send confirmation to the hardware processor that the data is written to their staging buffer, and write the data from their staging buffer to their non-volatile data storage device on receipt of a commit command.

公开(公告)号：US20170228233A1

公开(公告)日：2017-08-10

申请号：US15019112

申请日：2016-02-09

Applicant: INTEL CORPORATION

Inventor： Michael Mishaeli ,  Jason W. Brandt ,  Gilbert Neiger ,  Asit K. Mallick ,  Rajesh M. Sankaran ,  Raghunandan Makaram ,  Benjamin C. Chaffin ,  James B. Crossland ,  H. Peter Anvin

IPC: G06F9/30 ,  G06F13/40

CPC classification number: G06F9/3009 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/52 ,  G06F13/4068

Abstract: A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.