公开(公告)号：US11557085B2

公开(公告)日：2023-01-17

申请号：US17112792

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Soethiha Soe ,  Selvakumar Panneer ,  Adam Lake ,  Nilesh Jain ,  Deepak Vembar ,  Glen J. Anderson ,  Varghese George ,  Carl Marshall ,  Scott Janus ,  Saurabh Tangri ,  Karthik Veeramani ,  Prasoonkumar Surti

IPC: G06T7/20 ,  G06T17/00 ,  G06N3/04 ,  G06N3/08 ,  G06F3/01 ,  G06K9/62 ,  G06V30/262

Abstract: Embodiments are directed to neural network processing for multi-object three-dimensional (3D) modeling. An embodiment of a computer-readable storage medium includes executable computer program instructions for obtaining data from multiple cameras, the data including multiple images, and generating a 3D model for 3D imaging based at least in part on the data from the cameras, wherein generating the 3D model includes one or more of performing processing with a first neural network to determine temporal direction based at least in part on motion of one or more objects identified in an image of the multiple images or performing processing with a second neural network to determine semantic content information for an image of the multiple images.

公开(公告)号：US20220350751A1

公开(公告)日：2022-11-03

申请号：US17862739

申请日：2022-07-12

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Abhishek Appu ,  Aravindh Anantaraman ,  Valentin Andrei ,  Durgaprasad Bilagi ,  Varghese George ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Pattabhiraman K ,  SungYe Kim ,  Subramaniam Maiyuran ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Xinmin Tian

IPC: G06F12/123 ,  G06F12/0875 ,  G06F12/0891 ,  G06T1/60

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

公开(公告)号：US20220284867A1

公开(公告)日：2022-09-08

申请号：US17703645

申请日：2022-03-24

Applicant: Intel Corporation

Inventor： Arthur J. Runyan ,  Richmond Hicks ,  Nausheen Ansari ,  Narayan Biswal ,  Ya-Ti Peng ,  Abhishek R. Appu ,  Wen-Fu Kao ,  Sang-Hee Lee ,  Joydeep Ray ,  Changliang Wang ,  Satyanarayana Avadhanam ,  Scott Janus ,  Gary Smith ,  Nilesh V. Shah ,  Keith W. Rowe ,  Robert J. Johnston

IPC: G09G3/34 ,  G09G3/36 ,  B60R1/00 ,  G09G5/10 ,  G09G5/14 ,  G09G5/38 ,  G06F3/147 ,  G02B27/01 ,  G09G5/00

Abstract: Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.

公开(公告)号：US20220114108A1

公开(公告)日：2022-04-14

申请号：US17428529

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Abhishek Appu ,  Aravindh Anantaraman ,  Valentin Andrei ,  Durgaprasad Bilagi ,  Varghese George ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Pattabhiraman K. ,  SungYe Kim ,  Subramaniam Maiyuran ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Xinmin Tian

IPC: G06F12/123 ,  G06F12/0891 ,  G06F12/0875 ,  G06T1/60

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received.

公开(公告)号：US20210374897A1

公开(公告)日：2021-12-02

申请号：US17303654

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Scott Janus ,  Varghese George ,  Subramaniam Maiyuran ,  Altug Koker ,  Abhishek Appu ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Andrei Valentin ,  Ashutosh Garg ,  Yoav Harel ,  Arthur Hunter, JR. ,  SungYe Kim ,  Mike Macpherson ,  Elmoustapha Ould-Ahmed-Vall ,  William Sadler ,  Lakshminarayanan Striramassarma ,  Vikranth Vemulapalli

IPC: G06T1/20 ,  G06F9/50 ,  G06F12/0806 ,  G06F15/80 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06F7/544

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.

公开(公告)号：US11145105B2

公开(公告)日：2021-10-12

申请号：US16355364

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Arthur Hunter, Jr. ,  Kamal Sinha ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06T17/20

Abstract: Embodiments are generally directed to multi-tile graphics processor rendering. An embodiment of an apparatus includes a memory for storage of data; and one or more processors including a graphics processing unit (GPU) to process data, wherein the GPU includes a plurality of GPU tiles, wherein, upon geometric data being assigned to each of a plurality of screen tiles, the apparatus is to transfer the geometric data to the plurality of GPU tiles.

公开(公告)号：US20210218954A1

公开(公告)日：2021-07-15

申请号：US17252843

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Changliang Wang ,  Ximin Zhang ,  Jill Boyce ,  Sang-Hee Lee ,  Scott Janus ,  Yunbiao Lin

IPC: H04N19/102 ,  H04N19/146

Abstract: Embodiments are generally directed to transport controlled video coding. An embodiment of an apparatus includes one or more processors to process data; a memory to store data, including data for video streaming; and a video processing mechanism including an encoder and a transport mechanism, wherein the video processing mechanism is to generate a prediction of channel throughput for a network channel, encode one or more bitstreams based on the prediction, including encoding a plurality of bitstreams including a first bitstream and a second bitstream if the prediction indicates an increase or decrease in channel throughput and encoding a single bitstream if the prediction indicates a stable channel throughput; and select a bitstream of the one or more bitstreams for a current frame.

公开(公告)号：US10929948B2

公开(公告)日：2021-02-23

申请号：US16236110

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Carsten Benthin ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Philip Laws ,  Scott Janus

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/0862

Abstract: An apparatus and method for hardware page cache migration. For example, one embodiment of an apparatus comprises: a memory management unit (MMU) to manage memory page migration in multi-processor environments in which multiple processors share a virtual memory address space, the memory page migration comprising movement of one or more memory pages from a local memory of a first processor to a local memory of a second processor; a central page cache integral to or coupled to the MMU, the central page cache to store memory pages based on requests generated from one or more of the multiple processors; access pattern detection circuitry/logic to detect data access patterns associated with data access requests from one or more of the multiple processors; and an adaptive page prefetcher to prefetch one or more memory pages to the central page cache responsive to the access pattern detection circuitry/logic detecting one of the data access patterns.

公开(公告)号：US10911799B2

公开(公告)日：2021-02-02

申请号：US16050475

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Scott Janus ,  Prasoonkumar Surti ,  Stanley Baran ,  Michael Apodaca ,  Srikanth Potluri ,  Hugues Labbe ,  Jong Dae Oh ,  Gokcen Cilingir ,  Archie Sharma ,  Jeffrey Tripp ,  Jason Ross ,  Barnan Das

IPC: H04N21/435 ,  H04N21/235 ,  H04N21/845 ,  G06T15/00 ,  G06T15/80 ,  G06T15/50 ,  H04N21/2662

Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to decode point cloud data, reconstruct the decoded point cloud data and fill one or more holes in reconstructed point cloud frame data using patch metadata included in the decoded point cloud data and a memory communicatively coupled to the one or more processors.

公开(公告)号：US20200211152A1

公开(公告)日：2020-07-02

申请号：US16236110

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Carsten Benthin ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Philip Laws ,  Scott Janus

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/0862

Abstract: An apparatus and method for hardware page cache migration. For example, one embodiment of an apparatus comprises: a memory management unit (MMU) to manage memory page migration in multi-processor environments in which multiple processors share a virtual memory address space, the memory page migration comprising movement of one or more memory pages from a local memory of a first processor to a local memory of a second processor; a central page cache integral to or coupled to the MMU, the central page cache to store memory pages based on requests generated from one or more of the multiple processors; access pattern detection circuitry/logic to detect data access patterns associated with data access requests from one or more of the multiple processors; and an adaptive page prefetcher to prefetch one or more memory pages to the central page cache responsive to the access pattern detection circuitry/logic detecting one of the data access patterns.