中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

241 records (took 0.021 seconds)

    93.
    发明专利
    未知

    公开(公告)号：NO882687L

    公开(公告)日：1988-06-17

    申请号：NO882687

    申请日：1988-06-17

    Applicant: MOTOROLA INC

    Inventor： DAVIS WALTER LEE

    IPC: H04L25/02 ,  H04L25/38 ,  H04W8/24 ,  H04W88/02 ,  H04Q7/02

    Abstract: PCT No. PCT/US86/02199 Sec. 371 Date Nov. 4, 1986 Sec. 102(e) Date Nov. 4, 1986 PCT Filed Oct. 21, 1986 PCT Pub. No. WO88/03349 PCT Pub. Date May 5, 1988.A radio communication receiver decodes digital signals transmitted over a radio link and is capable of altering the bit rate of the receiver to match the bit rate transmitted form a remote location. The receiver includes a receiver portion 21 receiving radio signals and producing a received signal. A microporocessor 26 is used for decoding the received signal. The microprocessor (26) is responsive to a bit rate signal that is generated by a programmable divider (33). The microprocessor (26) is adpated to detect a predetermined code signal to alter the timing characteristic of the bit rate signal for generating a bit rate signal at a second rate for decoding received signals at a second bit rate designated by the predetermined code signal.

    DUAL DEADMAN TIMER CIRCUIT
    94.
    发明专利
    DUAL DEADMAN TIMER CIRCUIT 未知

    公开(公告)号：DE3176487D1

    公开(公告)日：1987-11-19

    申请号：DE3176487

    申请日：1981-08-21

    Applicant: MOTOROLA INC

    Inventor： DAVIS WALTER LEE ,  JACOBSON JAMES EVERETTE

    IPC: G06F1/00 ,  G06F1/24 ,  G06F1/32 ,  G06F9/00 ,  G06F11/00 ,  G06F11/14 ,  G06F11/30 ,  H04Q7/14

    Abstract: A dual deadman timer circuit functions to reset a dual mode microprocessor in the event of loss of program control. The microprocessor has high and low power requirements corresponding to its two operating modes, and the deadman timer circuit also adjusts the output power level of an associated two-level power supply to ensure that sufficient power is available for the full operation of the microprocessor during reset. The deadman timer functions during both microprocessor modes and includes two level-sensitive input sections to ensure that the microprocessor is reset under an error condition.

    95.
    发明专利
    未知

    公开(公告)号：DK302385D0

    公开(公告)日：1985-07-03

    申请号：DK302385

    申请日：1985-07-03

    Applicant: MOTOROLA INC

    Inventor： DAVIS WALTER LEE ,  HEROLD BARRY WAYNE ,  LITTLE WENDELL LEE

    IPC: G06F1/00 ,  G06F1/04 ,  G06F1/08 ,  G06F1/32 ,  G06F15/78 ,  H03L7/089 ,  H03L7/107 ,  H03L7/183 ,  G06F

    Abstract: A microcomputer (104) having predetermined clock pulse frequency requirements receives pulses from a multiplying type frequency synthesizer (200) which utilizes a reference frequency less than the largest of the predetermined requirements. The synthesizer (200) is responsive to program instructions to generate clock pulse frequencies sufficient to satisfy the requirement for immediate execution of programmed tasks. As the execution requirements change, the synthesizer (200) responds to provide only the frequency required. Thus, the power dissipated by the entire microcomputer system is minimized.

    96.
    发明专利
    未知

    公开(公告)号：BR8108824A

    公开(公告)日：1982-08-24

    申请号：BR8108824

    申请日：1981-08-31

    Applicant: MOTOROLA INC

    Inventor： DAVIS WALTER LEE ,  KRAUL DOUGLAS ROBERT

    IPC: G11C17/00 ,  G11C5/00 ,  G11C8/00 ,  G11C8/10 ,  G11C11/34 ,  G11C11/40 ,  G11C11/413

    Abstract: A memory system is used to store data and is powered-up by and only during accessing signals, thus using essentially no current when not being accessed. The memory system includes a decoding network using a mixture of NPN and PNP transistors, and a buffer circuit at the input to a memory cell array allows the use of a minimum number of select lines, having low power requirements.

    97.
    发明专利
    未知

    公开(公告)号：ES2191026T3

    公开(公告)日：2003-09-01

    申请号：ES94901673

    申请日：1993-11-23

    Applicant: MOTOROLA INC

    Inventor： DAVIS WALTER LEE

    IPC: H04B5/00 ,  H04W84/02 ,  H04B7/26

    Abstract: A cooperative paging system (10) and radio telephone system (15) combine to provide conventional delivery of short paging messages to a combination pager/radio telephone (40) via a first communication path, while a radio telephone link operating at a higher data rate is used to deliver large data messages to the pager/radio telephone (40). The radio telephone link is formed by a transceiver section (205) of the pager/radio telephone (40) coupling to a radio telephone base station (50,52) and calling up a paging terminal (32) of the paging system (10). The paging terminal (32) retrieves the large data messages from a temporary message memory (42) to deliver to the pager/radio telephone (40).

    98.
    发明专利
    未知

    公开(公告)号：AT222394T

    公开(公告)日：2002-08-15

    申请号：AT96923669

    申请日：1996-06-28

    Applicant: MOTOROLA INC

    Inventor： DAVIS WALTER LEE ,  HUANG JIAN-CHENG ,  JASINSKI LEON

    IPC: G10L19/00 ,  G10L19/02 ,  G10L19/04 ,  H03M7/30 ,  H04B14/04 ,  H04Q7/16 ,  H04W88/18 ,  G10L19/06

    Abstract: An apparatus and method for processing a voice message to provide low bit rate speech transmission processes the voice message to generate speech parameters which are arranged into a two dimensional parameter matrix (502) including a sequence of parameter frames. The two dimensional parameter matrix (502) is transformed using a predetermined two dimensional matrix transformation function (414) to obtain a two dimensional transform matrix (506). Distance values representing distances between templates of a set of predetermined templates and the two dimensional transform matrix (506) are then derived. The distance values derived are identified by indexes identifying the templates of the set of predetermined templates. The distance values derived are compared, and an index corresponding to a template of the set of predetermined templates having a shortest distance is selected and then transmitted.

Patent Agency Ranking