HORIZONTAL/CLOCK TIMING ERROR CORRECTION FOR INSET IMAGE

    公开(公告)号:AU6204686A

    公开(公告)日:1987-03-05

    申请号:AU6204686

    申请日:1986-08-28

    Applicant: RCA CORP

    Abstract: System performance of picture-in-picture video display systems is dependent on critical timing relationships between the incoming signals and the clock signals used to sample and display both the large picture and small picture signals. Video signals from various sources, e.g. VTR's, tend to have jittering time bases which may cause the small image to appear jagged or tilted. This distortion in the small image may be reduced by effecting adaptive signal delays in the small picture signal responsive to the relative phase of the system clock signal with respect to the horizontal synchronizing pulses of the large and/or small picture signal. One phase measure is used to control an interpolator which combines successive samples of the small picture signal in proportions to develop sample values corresponding to samples that would have occurred had the small picture signal been sampled by a clock properly aligned to the small picture horizontal synchronizing pulses. A second phase measure is used to delay the clock signal used to display the small picture so that the clock pulses that define the edges of the small picture occurs with the same timing relative to the large picture horizontal synchronizing pulses form line-to-line.

    92.
    发明专利
    未知

    公开(公告)号:DK418286A

    公开(公告)日:1987-03-04

    申请号:DK418286

    申请日:1986-09-02

    Applicant: RCA CORP

    Abstract: System performance of picture-in-picture video display systems is dependent on critical timing relationships between the incoming signals and the clock signals used to sample and display both the large picture and small picture signals. Video signals from various sources, e.g. VTR's, tend to have jittering time bases which may cause the small image to appear jagged or tilted. This distortion in the small image may be reduced by effecting adaptive signal delays in the small picture signal responsive to the relative phase of the system clock signal with respect to the horizontal synchronizing pulses of the large and/or small picture signal. One phase measure is used to control an interpolator which combines successive samples of the small picture signal in proportions to develop sample values corresponding to samples that would have occurred had the small picture signal been sampled by a clock properly aligned to the small picture horizontal synchronizing pulses. A second phase measure is used to delay the clock signal used to display the small picture so that the clock pulses that define the edges of the small picture occurs with the same timing relative to the large picture horizontal synchronizing pulses form line-to-line.

    TELEVISION DISPLAY SYSTEM WITH FLICKER REDUCTION

    公开(公告)号:GB2178267A

    公开(公告)日:1987-02-04

    申请号:GB8618101

    申请日:1986-07-24

    Applicant: RCA CORP

    Abstract: A speed-up memory doubles the field rate of a video input signal by repeating each field to reduce flicker when the double field rate signal is displayed. Read/write clocks for controlling the memory are locked to the color subcarrier of the video input signal thereby tending to produce visual artifacts in the displayed image due to clock skew relative to sync when non-standard video signals are processed. The skew errors are corrected by circuitry which measures the skew of the read and write clocks and delays the video signal as a function of a difference between the clock skew measurements.

    ANTI-ALIASING AND VIDEO PEAKING FILTER FOR PICTURE-IN- PICTURE DISPLAY

    公开(公告)号:AU5481386A

    公开(公告)日:1986-10-02

    申请号:AU5481386

    申请日:1986-03-18

    Applicant: RCA CORP

    Abstract: A pix-in-pix display includes a filtering system for processing the video signals which produce the reduced-size image. The filtering system includes an anti-aliasing filter - (210) which reduces the amplitude of the components of the video signals which may cause aliasing distortion when the image is subsampled. However, the filter passes substantial amounts of these components. The filtered video signal is subsampled (212) and applied to a peaking filter (220) which amplifies the band of frequencies containing the aliasing components relative to lower frequency bands to improve the appearance of detailed portions of the reproduced image.

    96.
    发明专利
    未知

    公开(公告)号:DE3544865A1

    公开(公告)日:1986-06-19

    申请号:DE3544865

    申请日:1985-12-18

    Applicant: RCA CORP

    Abstract: A digital input signal to be delayed is applied to a two-point linear interpolation filter which imparts delay to the signal proportional to the value of a delay control signal. Errors in both the amplitude and the phase of the delayed signal are minimized by the addition of a correction signal to the delayed signal. The correction signal is provided by applying the input signal to a further filter and a multiplier connected in cascade. The further filter is a linear phase filter having a response zero at zero frequency and a delay equal to an add multiple of one-half of the sampling period, Ts, of the digital input signal. The multiplier is controlled so as to vary the amplitude of the compensating signal as a non-linear function of the delay control signal so as to provide maximum amplitude compensation at delays corresponding to odd multiples of Ts/2 and zero amplitude compensation at delays equal to integer multiples of Ts.

    BIDIRECTIONAL DEFLECTOR DRIVER FOR VIDEO DISC

    公开(公告)号:CA1154160A

    公开(公告)日:1983-09-20

    申请号:CA364240

    申请日:1980-11-07

    Applicant: RCA CORP

    Abstract: -13- RCA 74,513 A bidirectional pulse generator for driving a video disc stylus deflector. Responsive to a deflection pulse a charge integrator has its input connected to a polarity selectable current source. The integrator generates a ramped potential output signal having an amplitude proportional to the deflection pulse width and a slope related to the current polarity. Upon termination of the deflection pulse a feedback loop is closed around the integrator to rapidly reset the output potential of the integrator to one of two pre-pulse output amplitudes. A direction control selects the current source polarity and controls the pre-pulse output amplitude and thereby the relative polarity of the output pulse.

    100.
    发明专利
    未知

    公开(公告)号:FR2498850A1

    公开(公告)日:1982-07-30

    申请号:FR8201337

    申请日:1982-01-28

    Applicant: RCA CORP

    Abstract: In a signal expander, the envelope of an input signal (S1) to be expanded is detected (30) and applied as a control signal (S3) to the gain control input (18) of a variable gain device (14) which expands the input signal. The control signal is applied to the variable gain device via an adaptive filter (40) having improved ripple reduction and transient performance characteristics to minimize audibility of gain changes. The adaptive filter includes a low pass filter (50,52) for producing a smoothed control signal essentially free of ripple and an analog gate (70,74,78) for coupling the greater of the smoothed signal or a further signal to the variable gain device, the further signal being equal to the detector output signal less a constant. Compression of an input signal is provided by applying the input signal to the non-inverting input (110) fig 3 not shown of an amplifier (100) and feeding the (compressed) output signal (S1) of the amplifier to the expander (30,40, 14) and feeding the output signal (S2) of the expander to the inverting input of the amplifier (100).

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