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公开(公告)号：JPS60107A
公开(公告)日：1985-01-05
申请号：JP10718083
申请日：1983-06-15
Applicant: SONY CORP
Inventor： SONEDA MITSUO , MAEKAWA TOSHIICHI
IPC: H03F3/45
Abstract: PURPOSE:To improve the linearity of a differential amplifier by preventing the variation of the drain-source resistance due to the voltage of an input signal. CONSTITUTION:An input signal source 11 is differentially connected to the gates of MOSFETs 1 and 2 having sources connected in common to each other, and a constant current source 12 is connected to the source common juncture. Thus a differential amplifier is obtained. While a standard differential amplifier is constituted by MOSFETs 7 and 8 having gates connected differentially with the source 11. The drain of the FET1 is connected to the source of an MOSFET3; while the gate of the FET3 is connected to the drain of the FET7. The drain of the FET2 is connected to the source of an MOSFET4; while the gate of the FET4 is connected to the drain of the FET8. In such a constitution, the drain- source voltage of FETs 1 and 2 which amplify the input signal has no change due to the input voltage. Thus, the variation of each drain-source voltage due to the level of the input signal is prevented.
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公开(公告)号：JPS58171850A
公开(公告)日：1983-10-08
申请号：JP5462482
申请日：1982-03-31
Applicant: SONY CORP
Inventor： SONEDA MITSUO , MAEKAWA TOSHIICHI , OOTSU KOUJI
Abstract: PURPOSE:To prevent the phenomena of blooming and smears by a method wherein P channel MOSFETs are used as the switching elements of a solid-state image pickup elements. CONSTITUTION:The solid-state image pickup element 20 has an image pick-up surface constituted of image pickup picture elements E'll-E'mn. The image pickup picture elements E'll-E'mn are formed of photoelectric conversion parts Dll-Dmn and the P channel type MOSFETs S'll-S'mn, then the drain of each of the MOSFETs S'll-S'mn is connected respectively to the photoelectric conversion parts Dll-Dmn, the gates of those constituting the row in each horizontal direction of the MOSFETs S'll-S'mn are connected in common, and respectively connected to control terminals vl-vm. The sources of those constituting the row in the vertical direction are connected in common, and respectively connected to each source of N channel MOSFETs Tl-Tn. Even when the drain potential of the MOSFET S' decreases more than that of an N type well, accompanied by the accumulation of signal charges, a parasitic transistor constituted of drains, N type wells, and sources does not conduct.
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公开(公告)号：JPS58131766A
公开(公告)日：1983-08-05
申请号：JP1376982
申请日：1982-01-30
Applicant: SONY CORP
Inventor： YAMANAKA SEISUKE , SONEDA MITSUO , MAEKAWA TOSHIICHI
Abstract: PURPOSE:To eliminate the need for a mechanical shutter by arranging an photoelectric transducer section connected to a first switching element and a second switching element connected to the transducer section, excluding charges when the second switching element is under an opened state and obtaining signal charges when the element is under a closed state. CONSTITUTION:When beams are projected to a solid-state image pickup element 1, photoelectric transduction is executed in the photoelectric transducer sections D11-Dmn, and charges corresponding to luminous energy projected to the pickup picture element are generated. Signal charges are obtained when the charges generated are stored into the sources of MOS.FETs S11-Smn, but charges generated are excluded to connecting lines connecting drains and a power supply 20 and are not stored into the sources of the S11-Smn when MOS. FETs Q11-Qmn are under opened states. When the Q11-Qmn are under closed states, on the other hand, the charges generated are stored into the sources with the exception of the case when the S11-Smn are under opened states, and signal charges are acquired. Accordingly, a shutter is closed when the Q11-Qmn are under opened states, and opened when the Q11-Qmn are under closed states in succession at the same time or selectively, and an electronic shutter is formed.
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公开(公告)号：JPS57201295A
公开(公告)日：1982-12-09
申请号：JP8628981
申请日：1981-06-04
Applicant: SONY CORP
Inventor： SONEDA MITSUO , OOTSU KOUJI
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公开(公告)号：JPS57192178A
公开(公告)日：1982-11-26
申请号：JP7717481
申请日：1981-05-21
Applicant: SONY CORP
Inventor： SONEDA MITSUO
Abstract: PURPOSE:To obtain an output signal having large amplitude with a simple constitution, by sampling a tie division current from a device and supplying to a capacitor and supplying the charge of the capacitor to a capacitor with a small capacitance than that of the capacitor via an active charge transfer device. CONSTITUTION:A signal current is from a horizontal signal transmission line LH of a device IM represents a time dividing signal which is obtained from a signal charge Qs of each picture element with sequential sampling, and the amount of current flowing in one scanning period corresponds to a charge Q3. This current is is received with a capacitor 11 of a comparatively large capacitance and the charge is transferred to a capacitor 12 of a comparatively small capacitance via a charge transfer device 13 consisting of a MOS transistor TR15 which is active in the saturated region. The terminal voltage of the capacitor 12 is outputted via an output device 14 consisting of a source follower type MOSFET and the like.
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Patent Agency Ranking
公开(公告)号：JPS57190467A
公开(公告)日：1982-11-24
申请号：JP7480981
申请日：1981-05-20
Applicant: SONY CORP
Inventor： SONEDA MITSUO , NOGUCHI TAKASHI , OOTSU KOUJI
IPC: H04N5/20 , H03G1/00 , H04N5/243 , H04N5/335 , H04N5/353 , H04N5/355 , H04N5/357 , H04N5/372 , H04N5/374 , H04N5/378
Abstract: PURPOSE:To sharply improve SN and resolution by supplying time-shared signal current obtained from a signal transmission line to a current amplifier type gain control amplifier circuit and converting the output current into voltage to take up the voltage. CONSTITUTION:Respective picture elements SO11-SOnm and SE11-SEnm in a photodetecting part 1 are successively scanned and the signal charge of a scanned and selected picture element is taken out from a signal transmission line LH to obtain time charging differential signal curent is. The current is is directly inputted to a current injection type gain control amplifier circuit 10 consisting of transistors TR11-15 and amplified while being gain-controlled. By said constitution, the signal charge is completely transferred to horizontal/ vertical lines without remaining charge even if the output resistance RL value of the circuit 10 is increased, preventing the titled circuit from bad influence such as the deterioration of resolution independently of the high resistance RL value. In addition, current is directly amplified without using a preamplifier or the like to obtain an output voltage signal with wide amplitude, improving SN sharply.
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公开(公告)号：JPS57121311A
公开(公告)日：1982-07-28
申请号：JP740281
申请日：1981-01-21
Applicant: Sony Corp
Inventor： SONEDA MITSUO
Abstract: PURPOSE: To control the gain by a current or a voltage, by connecting complementary transistors, which have diodes between bases and collectors, to emitters of both transistors of a current mirror circuit.
CONSTITUTION: Transistors (TR) 13 and 14 which have TRs 15 and 16 of diode connection between their own bases and collectors are connected to emitters of TRs 11 and 12 constituting a current mirror. FETs 17 and 18 which operate as a current source are connected to bases of TRs 13 and 14, and a signal source 21 and DC power sources 19 and 20 are connected to gates of FETs 17 and 18. A current ID
1 flowed to the TR 15 of diode connection is controlled by the signal source 21 to control the gain of an output current IOUT for an input current IIN.
COPYRIGHT: (C)1982,JPO&JapioAbstract translation: 目的：通过将在基极和集电极之间具有二极管的互补晶体管连接到电流镜电路的两个晶体管的发射极来控制电流或电压的增益。 构成：在它们自己的基极和集电极之间具有二极管连接的TR 15和16的晶体管（TR）13和14连接到构成电流镜的TR11和12的发射极。 作为电流源工作的FET 17和18连接到TR13和14的基极，信号源21和DC电源19和20连接到FET 17和18的栅极。电流ID1流到TR 15 二极管连接的控制由信号源21控制输入电流I IN的输出电流IOUT的增益。
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公开(公告)号：JPS56169922A
公开(公告)日：1981-12-26
申请号：JP7469280
申请日：1980-06-03
Applicant: SONY CORP
Inventor： SONEDA MITSUO
IPC: H03H15/02
Abstract: PURPOSE:To make the constitution easy and to prevent the deterioration of DG, DP, by connecting a common clock driving circuit and separate auxiliary clock driving circuit to charge transfer capacitive elements, and picking up an output signal from the auxiliary clock driving circuit. CONSTITUTION:In a BBD10, between terminals of a charge transfer capacitive element to pick up the signal of a clock signal phi1 system, that is, delay output terminals (a) and (b) introduced from the hot end of capacitors C2, C6, an additional capacitive element of the capacitance in response to the coefficient of sensitivity, i.e. a capacitor CA is connected. Further, an output terminal 12 is given from the coil end side of the capacitor C2. A separate auxiliary clock driving terminal 15 as a common clock driving circuit of the BBD10 consists of transistors (TR) Qa, Qb, and an input terminal 16 is introduced commonly from each base of the TRs Qa, Qb, and each emitter is connected commonly to the output terminal 12. A clock signal phi1' in phase of synchronized clock signal phi1 is fed to the input terminal 16 and the clock signal phi1 is outputted to the output terminal.
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公开(公告)号：JPS56165988A
公开(公告)日：1981-12-19
申请号：JP7058080
申请日：1980-05-27
Applicant: SONY CORP
Inventor： TSUCHIYA TAKAHISA , SONEDA MITSUO
IPC: G11C27/04 , G11C19/18 , H01L21/339 , H01L29/762
Abstract: PURPOSE:To prevent the production of cross-talk with a simple constitution and to improve the switching characteristic, by separating, a clock signal circuit for every charge transfer element, and providing the same with a clock drive circuit. CONSTITUTION:Charge transfer elements BBD1-BBD3 such as BBD are provided with separated and independent clock signal lines respectively, and a clock signal is fed with a clock drive circuit consisting of FETs 191-241, 192-242 and 193-243 connected to a clock generating source 8 to drive the BBD1-BBD3. With this constitution, even in case of connection of the BBD3, at the post stage of the BBD1 via selector switches 27, 28, no cross talk with the BBD2 via the clock signal line such as the case with a common clock signal line is produced and the switching performance is improved with a simple constitution.
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公开(公告)号：JPS56160067A
公开(公告)日：1981-12-09
申请号：JP5260580
申请日：1980-04-21
Applicant: SONY CORP
Inventor： TSUCHIYA TAKAHISA , SONEDA MITSUO , NAKAMURA ISA
IPC: G11C27/04 , G11C19/18 , H01L21/339 , H01L29/762 , H03H15/02
Abstract: PURPOSE:To satisfactorily process the signals in a simple construction by a method wherein differences in the speeds in a current mirror circuit are corrected, in the signal processing circuit adapted to mix up a plurality of signals respectively through the current mirror circuit. CONSTITUTION:In BBD comprising a transistor (Tr) having an input terminal 1, clock terminals 6, 7, NPN type Tr.Q1, Q2... and capacitors C0, C1..., the plurality of the signals are taken out, being mixed up through the current mirror circuit and signal-processed. The current mirror circuit M1 with the P type elements is formed by connecting a collector of the Tr.11 with a base of the PNP type Tr.21, an emitter of the Tr.21 with a collector and base of the PNP type Tr.22, a base of the Tr.23 with a base of the Tr.22, a collector of the Tr.23 with the collector of the Tr.11, and emitters of the Tr.22, 23 with a source terminal 4. In addition, the collector of the Tr.21 is connected to a hot end side of the capacitor C1.
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