公开(公告)号：EP0971416A4

公开(公告)日：2000-08-09

申请号：EP99901180

申请日：1999-01-26

Applicant: SONY CORP

Inventor： GOSAIN DHARAM PAL ,  NOMOTO KAZUMASA ,  WESTWATER JONATHAN ,  NAKAGOE MIYAKO ,  USUI SETSUO ,  NOGUCHI TAKASHI ,  MORI YOSHIFUMI

IPC: H01L21/8247 ,  B82B1/00 ,  H01L21/28 ,  H01L21/822 ,  H01L21/84 ,  H01L27/10 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC classification number: B82Y10/00 ,  H01L21/28273 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7883 ,  H01L29/792

Abstract: An accumulation region (15) comprises many dispersed dots (15a) whose surface density is higher than that of structural pin-holes produced in a tunnel insulating film (14a). Alternatively, the number of dots (15a) in the accumulation region (15) is determined to be five or more. Alternatively, a conduction region (13c) is formed in a polysilicon layer (13) whose surface roughness is greater than 0.1 nm and less than 100 nm. The number of dots (15a) in the accumulation region (15) is larger than the number of grains in the conduction region (13c). Even if defects, such as pin-holes, occur in the tunnel insulating film (14a) and charges accumulated in some dots leak, the charges accumulated in the dots in the regions where no defect is present do not leak. Therefore, information can be held for a long time.

Abstract translation: 虽然存储区15由许多分散微粒（点）（15A）的，颗粒（15A）的表面密度被设置为比在隧道产生的构造性的孔（针孔）的更高的绝缘膜 - （14a）的 ，或在存储区域（15）的微粒（15A）的数量设定为5个以上。 虽然传导区（13C）由具有0.1纳米的表面粗糙度〜100nm的多晶硅层（13）形成的，在所述存储区域中的颗粒（15A）根据（15）的数量被设定为比数大 在传导区（13c）中的晶粒。 即使当缺陷：例如销孔中的隧道绝缘膜 - （14a）的发生，并存储在所述颗粒的部分电荷被泄露，存储在其中不存在缺陷的发生不被泄漏的区域中形成的微粒的电荷。 因此，信息可以保持很长一段时间。

公开(公告)号：DE3540452C2

公开(公告)日：1999-07-29

申请号：DE3540452

申请日：1985-11-14

Applicant: SONY CORP

Inventor： HAYASHI HISAO ,  NOGUCHI TAKASHI

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/324 ,  H01L21/336 ,  H01L27/12 ,  H01L29/786

Abstract: A method of manufacturing a thin film transistor comprises forming a thin polycrystalline semiconductor film 4 on a substrate 1, implanting ions in the thin polycrystalline semiconductor film to form a thin amorphous semiconductor film, forming a gate insulating film 8 and a gate electrode 7 on the thin amorphous semiconductor film, doping impurities for forming source and drain regions 9, 10 in the thin amorphous semiconductor film using the gate electrode 7 and the gate insulating film 8 as masks, and performing annealing for solid-phase growing the thin amorphous semiconductor film and at the same time for electrically activating the impurities to form the source and drain regions 9, 10.

公开(公告)号：FR2573248A1

公开(公告)日：1986-05-16

申请号：FR8516906

申请日：1985-11-15

Applicant: SONY CORP

Inventor： HAYASHI HISAO ,  NOGUCHI TAKASHI

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/324 ,  H01L21/336 ,  H01L27/12 ,  H01L29/786

Abstract: A method of manufacturing a thin film transistor comprises forming a thin polycrystalline semiconductor film 4 on a substrate 1, implanting ions in the thin polycrystalline semiconductor film to form a thin amorphous semiconductor film, forming a gate insulating film 8 and a gate electrode 7 on the thin amorphous semiconductor film, doping impurities for forming source and drain regions 9, 10 in the thin amorphous semiconductor film using the gate electrode 7 and the gate insulating film 8 as masks, and performing annealing for solid-phase growing the thin amorphous semiconductor film and at the same time for electrically activating the impurities to form the source and drain regions 9, 10.

公开(公告)号：DE3268474D1

公开(公告)日：1986-02-27

申请号：DE3268474

申请日：1982-03-04

Applicant: SONY CORP

Inventor： NISHIMURA TOSHIMICHI ,  NOGUCHI TAKASHI

IPC: G11C19/28 ,  H03K3/286 ,  H03K5/02 ,  H03K17/66 ,  H04N5/335 ,  H04N5/3725 ,  H04N5/378

Abstract: A drive circuit comprises output transistors (Q 13 , Q 14 ) of complementary type serially coupled to each other between voltage supply terminals (+B, -B), auxiliary transistors (Q 16 , Q1 7 ) of complementary type which have base electrodes respectively connected to the serial connection point between the output transistors (Q 13 , Q 14 ) and which are serially coupled between the respective base electrodes of the output transistors (Q 13 , Q 14 ), and resistors (R 12 , R 13 ) serially coupled between the voltage supply terminals (+B, -8) with their connection point coupled to the connection point of the auxiliary transistors (Q 15 , Q 16 ), an input clock signal being supplied to the respective base electrodes of the output transistors (Q 13 , Q 14 ) via coupling capacitors (C 11 , C 13 ).

公开(公告)号：EP1345260A4

公开(公告)日：2008-05-28

申请号：EP01994979

申请日：2001-12-20

Applicant: SONY CORP

Inventor： YAMAGATA HIDEO ,  KOUMOTO TAKEYOSHI ,  ATSUUMI KENJI ,  NEGORO YOICHI ,  HIRATA TATSUSHIRO ,  NOGUCHI TAKASHI

IPC: H01L21/205 ,  C23C16/22 ,  C30B25/02 ,  H01L21/20 ,  H01L21/331 ,  H01L29/73 ,  H01L29/737

CPC classification number: H01L21/02505 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/66242

Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer. Thus, there can be obtained a semiconductor layer in which a misfit dislocation can be improved.

公开(公告)号：CA1315421C

公开(公告)日：1993-03-30

申请号：CA575400

申请日：1988-08-23

Applicant: SONY CORP

Inventor： HAYASHI HISAO ,  NEGISHI MICHIO ,  NOGUCHI TAKASHI ,  OHSHIMA TAKEFUMI ,  HAYASHI YUJI ,  MAEKAWA TOSHIKAZU ,  MATSUSHITA TAKESHI

IPC: H01L29/78 ,  H01L29/786

Abstract: A thin film MOS transistor has a construction which can minimize scattering of electrons and thus maximize electron mobility for allowing higher speed operation of the transistor. Toward this, the MOS transistor has a thin film form semiconductor layer having a thickness in a range less than or equal to 100 nm, between a pair of gate electrodes which oppose to each other across the semiconductor layer.

公开(公告)号：FR2573916B1

公开(公告)日：1991-06-28

申请号：FR8517451

申请日：1985-11-26

Applicant: SONY CORP

Inventor： NOGUCHI TAKASHI ,  HAYASHI HISAO ,  OHSHIMA TAKEFUMI

IPC: H01L21/20 ,  H01L21/265 ,  H01L29/786 ,  H01L29/04 ,  H01L29/68 ,  C30B1/00

Abstract: A method of forming a thin semiconductor film has the steps of: forming a thin semiconductor film on a predetermined substrate; implanting predetermined ions in the thin semiconductor film to convert the thin semiconductor film to a thin amorphous semiconductor film; decreasing a thickness of the thin amorphous semiconductor film to a predetermined thickness; and annealing the thin amorphous semiconductor film to cause solid-phase growth. According to this method, a large thin polycrystalline semiconductor film with a crystal grain size larger than the conventional crystal grain size and a good crystal grain orientation can be uniformly formed at a low temperature. It is, therefore, possible to use such a thin semiconductor film to fabricate a thin film semiconductor device with excellent electrical characteristics.

公开(公告)号：FR2506546B1

公开(公告)日：1988-11-04

申请号：FR8208913

申请日：1982-05-21

Applicant: SONY CORP

Inventor： SONEDA MITSUO ,  NOGUCHI TAKASHI ,  OHTSU TAKAJI

IPC: H03G1/00 ,  H04N5/243 ,  H04N5/335 ,  H04N3/15

公开(公告)号：FR2573916A1

公开(公告)日：1986-05-30

申请号：FR8517451

申请日：1985-11-26

Applicant: SONY CORP

Inventor： NOGUCHI TAKASHI ,  HAYASHI HISAO ,  OHSHIMA TAKEFUMI

IPC: H01L21/20 ,  H01L21/265 ,  H01L29/786 ,  H01L29/04 ,  H01L29/68 ,  C30B1/00

Abstract: A method of forming a thin semiconductor film has the steps of: forming a thin semiconductor film on a predetermined substrate; implanting predetermined ions in the thin semiconductor film to convert the thin semiconductor film to a thin amorphous semiconductor film; decreasing a thickness of the thin amorphous semiconductor film to a predetermined thickness; and annealing the thin amorphous semiconductor film to cause solid-phase growth. According to this method, a large thin polycrystalline semiconductor film with a crystal grain size larger than the conventional crystal grain size and a good crystal grain orientation can be uniformly formed at a low temperature. It is, therefore, possible to use such a thin semiconductor film to fabricate a thin film semiconductor device with excellent electrical characteristics.

公开(公告)号：FR2506546A1

公开(公告)日：1982-11-26

申请号：FR8208913

申请日：1982-05-21

Applicant: SONY CORP

Inventor： SONEDA MITSUO ,  NOGUCHI TAKASHI ,  OHTSU TAKAJI

IPC: H03G1/00 ,  H04N5/243 ,  H04N5/335 ,  H04N3/15