公开(公告)号：EP0616332B1

公开(公告)日：1999-06-23

申请号：EP93830109.0

申请日：1993-03-18

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Crisenza, Giuseppe ,  Dallabora, Marco

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0416 ,  G11C16/04 ,  G11C16/30

公开(公告)号：EP0920023A1

公开(公告)日：1999-06-02

申请号：EP97830625.6

申请日：1997-11-26

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino

IPC: G11C8/00 ,  G11C16/06

CPC classification number: G11C16/08

Abstract: The row decoder comprises a plurality of pre-decoding circuits (14, 15) which, starting from row addresses, generate pre-decoding signals and a plurality of final decoding circuits (12) which, starting from the pre-decoding signals, drive the individual rows of the array (2). Each pre-decoding circuit (10) has a push-pull output circuit with a pull-up transistor (42) and a pull-down transistor (44) and four parallel paths for the signal, a first path (50), supplied with low voltage, which drives the pull-up transistor during reading; a second path (52), supplied with a positive high voltage, which drives the pull-up transistor during programming and erasing; a third path (100), supplied with a low voltage, which drives the pull-down transistor during reading and programming; and a fourth path (102), supplied with a negative high voltage, which drives the pull-down transistor during erasing. Two selection stages (54, 104) enable selectively one of the first and second path (50, 52), and one of the third and fourth path (100, 102), depending on the operative step.

Abstract translation: 行解码器包括预解码电路（14，15）的复数，从行地址开始，生成预解码信号和最终解码电路的多个（12）其中，从预译码信号开始，驱动 该阵列的各行（2）。 每个预解码电路（10）具有与提供一个上拉晶体管（42）和一个下拉晶体管（44）和用于将信号四个平行路径，第一路径（50）的推挽输出电路 低电压，其读取期​​间驱动所述上拉晶体管; 具有正的高电压，其驱动编程和擦除期间，上拉晶体管提供第二路径（52）; 具有低电压，其读出和编程期间驱动所述下拉晶体管提供的第三路径（100）; 和第四路径（102），提供有负的高电压，其擦除期间驱动下拉晶体管。 两个选择阶段（54，104）使能选择性地将第一和第二路径中的一个（50，52）和所述第三和第四路径中的一个（100,102），根据操作步骤。