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公开(公告)号：EP0753859B1
公开(公告)日：2000-01-26
申请号：EP95830302.6
申请日：1995-07-14
Applicant: STMicroelectronics S.r.l.
Inventor： Sali, Mauro , Dallabora, Marco , Carrera, Marcello
CPC classification number: G11C16/3459 , G06F2201/81 , G11C16/04 , G11C16/3454 , G11C29/028 , G11C29/50 , G11C2029/5006
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公开(公告)号：EP0616333B1
公开(公告)日：1999-06-23
申请号：EP93830110.8
申请日：1993-03-18
Applicant: STMicroelectronics S.r.l.
Inventor： Campardo, Giovanni , Crisenza, Giuseppe , Dallabora, Marco
CPC classification number: G11C16/04 , G11C16/0416 , G11C16/30
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3.发明授权Electrically erasable and programmable non-volatile memory device with testable redundancy circuits 失效与可测试冗余电路电可擦除和可编程的非易失性存储器设备
公开(公告)号：EP0806773B1
公开(公告)日：2003-03-19
申请号：EP96830267.9
申请日：1996-05-09
Applicant: STMicroelectronics S.r.l.
Inventor： Dallabora, Marco , Villa, Corrado , Defendi, Marco
IPC: G11C29/00
CPC classification number: G11C29/24 , G11C29/02 , G11C29/44 , G11C29/824
Abstract: An electrically erasable and programmable non-volatile memory device comprises at least one memory sector (S1-S8) comprising an array of memory cells (MC) arranged in rows (WL0-WL255) and first-level columns (BL0-BL255), the first-level columns (BL0-BL255) being grouped together in groups of first-level columns each coupled to a respective second-level column (B1-B64), first-level selection means (2) for selectively coupling one first-level column for each group to the respective second-level column, second-level selection means (3,4) for selecting one of the second-level columns, first direct memory access test means (SW6) activatable in a first test mode for directly coupling a selected memory cell (MC) of the array to a respective output terminal (Oi) of the memory device, redundancy columns (RBL0-RBL3) of redundancy memory cells (RMC) for replacing defective columns (BL0-BL255) of memory cells (MC), and a redundancy control circuit (CAM1-CAM4,5-7,12,SW1-SW5,24) comprising defective-address storage means (CAM1-CAM4) for storing addresses of the defective columns (BL0-BL255) and activating respective redundancy columns (RBL0-RBL3) when the defective columns are addressed. The redundancy control circuit comprises second direct memory access test means (24) activatable in a second test mode together with the first direct memory access test means for directly coupling memory elements (AB0-AB7,GB) of the defective-address storage means (CAM1-CAM4) to respective second-level columns (B1-B64) of the array, whereby the memory elements of the defective-address storage means can be directly coupled to output terminals (Oi) of the memory device.
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公开(公告)号：EP0676816B1
公开(公告)日：2001-10-04
申请号：EP94830144.5
申请日：1994-03-28
Applicant: STMicroelectronics S.r.l.
Inventor： Dallabora, Marco , Sali, Mauro Luigi , Tassan, Caser Fabio , Villa, Corrado
IPC: H01L29/788 , H01L27/115 , G11C16/04 , G11C16/06
CPC classification number: G11C16/16 , G11C16/0416 , H01L27/115 , H01L29/7885
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5.发明授权Erase voltage control circuit for an electrically erasable non-volatile memory cell 失效擦除电压控制电路，用于可擦除，非易失性存储器单元
公开(公告)号：EP0786779B1
公开(公告)日：2004-07-28
申请号：EP96830025.1
申请日：1996-01-24
Applicant: STMicroelectronics S.r.l.
Inventor： Villa, Corrado , Dallabora, Marco , Cane, Marcello
IPC: G11C16/06
CPC classification number: G11C16/14
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Patent Agency Ranking6.发明授权Method to prevent disturbances during the programming and erasing phases in a non-volatile memory device 失效在编程期间防止干扰和非易失性存储器的擦除的方法
公开(公告)号：EP0782148B1
公开(公告)日：2003-02-26
申请号：EP96830245.5
申请日：1996-04-30
Applicant: STMicroelectronics S.r.l.
Inventor： Dallabora, Marco , Villa, Corrado , Bartoli, Simone , Defendi, Marco
IPC: G11C16/06
CPC classification number: G11C16/344 , G11C16/10 , G11C16/16 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459
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公开(公告)号：EP0756286B1
公开(公告)日：2000-01-26
申请号：EP95830317.4
申请日：1995-07-24
Applicant: STMicroelectronics S.r.l.
Inventor： Dallabora, Marco , Villa, Corrado , Bettini, Luigi
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8.发明公开Method to prevent disturbances during the erasing phase in a non-volatile memory device 失效防止干扰的非易失性存储器的删除期间的方法
公开(公告)号：EP1260989A3
公开(公告)日：2005-11-30
申请号：EP02015769.9
申请日：1996-04-30
Applicant: STMicroelectronics S.r.l.
Inventor： Dallabora, Marco , Villa, Corrado , Bartoli, Simone , Defendi, Marco
CPC classification number: G11C16/344 , G11C16/10 , G11C16/16 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459
Abstract: The invention concerns a method of avoiding disturbance during an erasing steps of an electrically programmable and erasable, semiconductor integrated non-volatile memory device, which comprises a matrix of memory cells divided into sectors. An operation of parallel erasing several sectors of the matrix as well as an operation of verifying the erasing of each sector in the matrix are carried out.
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9.发明授权Method for erasing an electrically programmable and erasable non-volatile memory cell 失效擦除电可编程可擦除非易失性存储器单元的方法
公开(公告)号：EP0786778B1
公开(公告)日：2003-11-12
申请号：EP96830024.4
申请日：1996-01-24
Applicant: STMicroelectronics S.r.l.
Inventor： Villa, Corrado , Bez, Roberto , Cantarelli, Daniele , Dallabora, Marco
IPC: G11C16/06
CPC classification number: G11C16/14
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10.发明公开Method to prevent disturbances during the erasing phase in a non-volatile memory device 失效防止干扰的非易失性存储器的删除期间的方法
公开(公告)号：EP1260989A2
公开(公告)日：2002-11-27
申请号：EP02015769.9
申请日：1996-04-30
Applicant: STMicroelectronics S.r.l.
Inventor： Dallabora, Marco , Villa, Corrado , Bartoli, Simone , Defendi, Marco
CPC classification number: G11C16/344 , G11C16/10 , G11C16/16 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459
Abstract: The invention concerns a method of avoiding disturbance during an erasing steps of an electrically programmable and erasable, semiconductor integrated non-volatile memory device, which comprises a matrix of memory cells divided into sectors. An operation of parallel erasing several sectors of the matrix as well as an operation of verifying the erasing of each sector in the matrix are carried out.
Abstract translation: 本发明涉及在擦除电可编程且可擦除，半导体集成电路的非易失性存储器设备，其包括存储单元划分为扇区的矩阵的步骤期间避免干扰的方法。 在关于业务验证矩阵中的每个扇区的擦除的基质的平行擦除若干个扇区的以及手术被执行。
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