公开(公告)号：DE19750965A1

公开(公告)日：1999-06-02

申请号：DE19750965

申请日：1997-11-18

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  LUR WATER ,  SUN SHIH-WEI

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: A method of providing increased capacitance to a charge storage structure in an integrated circuit comprises providing an access circuit, in and on a substrate, which controls access to an electrode of the structure through an electrode contact. A first conductive layer is provided over the substrate and connected to the electrode contact, and a layer of dielectric material is provided over the conductive layer. A layer of grains of polysilicon is provided over the layer of dielectric material so as to leave uncovered portions between the grains, which are selectively removed to form spaced apart columns of dielectric material extending above the first conductive layer. A conformal second conductive layer is provided over the columns followed by a capacitor dielectric layer and a third conductive layer.

公开(公告)号：NL1007477C2

公开(公告)日：1999-05-10

申请号：NL1007477

申请日：1997-11-07

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  LUR WATER ,  SUN SHIH-WEI

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: A high capacitance charge storage capacitor for a DRAM has a lower electrode in contact with one source/drain region of a transfer FET. The lower capacitor electrode includes a first layer of polysilicon deposited over part of the transfer FET and in contact with the source/drain region of the transfer FET. An oxide layer is deposited over the first polysilicon layer and then a sparse layer of hemispherical grained polysilicon is deposited on the surface of the oxide layer. The sparse layer of hemispherical grained polysilicon has grains on the order of approximately 100 nanometers across that are separated on the average by approximately 100 nanometers. The layer of oxide is etched using the sparse grains of hemispherical grained polysilicon as a mask, with the etch process stopping on the surface of the first layer of polysilicon. A second layer of polysilicon is deposited over the remaining grains of hemispherical grained polysilicon and over the column-shaped portions of the oxide layer left by the etching stop. A capacitor dielectric is formed over the second layer of polysilicon and then an upper capacitor electrode is provided.

公开(公告)号：DE19745856A1

公开(公告)日：1999-04-22

申请号：DE19745856

申请日：1997-10-16

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI ,  YEW TRI-RUNG

IPC: H01L21/8242

Abstract: An IC component, with an embedded memory and logic circuits on a single substrate, is produced by forming a contact opening in a conformal protective layer (129), which covers transmission and logic FETs (104, 120), to expose a source or drain region (118) of one of the transmission FETs (104), forming a charge storage capacitor (130, 132, 134) connected to this source or drain region (118) and then removing the protective layer (129) at least from the logic circuit regions. Production of an integrated circuit component, which includes an embedded memory and logic circuits on a single substrate, comprises: (i) forming a substrate (100) with transmission FETs (104) in and on embedded DRAM regions and with logic FETs (120) in and on logic circuit regions; (ii) forming a conformal protective layer (129) over the FETs (104, 120), the layer having the same thickness over the gate electrodes and the source/drain regions (128) of the logic FETs (120); (iii) removing a portion of the protective layer (129) to form a contact opening which exposes a source or drain region (118) of one of the transmission FETs (104); (iv) forming a lower capacitor electrode (130) in contact with the source/drain region (118) of the transmission FET (104); (v) successively forming a capacitor dielectric layer (132) and an upper capacitor electrode (134) above the lower capacitor electrode (130) to form a charge storage capacitor for the transmission FET (104); and (vi) removing the protective layer (129) at least from the logic circuit regions. An Independent claim is also included for production of a similar integrated circuit component, in which the embedded memory is an embedded DRAM.

公开(公告)号：GB2327810A

公开(公告)日：1999-02-03

申请号：GB9715880

申请日：1997-07-28

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI ,  TSAI MENG-JIN

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/316 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/285 ,  H01L27/088

Abstract: Different thicknesses of gate oxide can be formed on a single chip in a single oxidation process by selectively implanting a dopant such as nitrogen into the surface of the chip in a pattern corresponding to the desired differences in gate oxide thickness. Implanting nitrogen to a silicon substrate reduces the rate at which oxide grows on the surface. Thus, by implanting different dosages of nitrogen into the surface of the substrate, thicker or thinner oxide layers can be provided. A processing chip with embedded DRAM can then be formed where the logic circuitry has a thin gate oxide and the DRAM circuitry has a thick gate oxide by implanting the higher dosage of nitrogen into the region of the chip where the logic circuits are to be formed. Different gate oxide thicknesses are then provided by exposing both the logic circuitry and the embedded DRAM section to a single thermal oxidation process.

公开(公告)号：GB2326524A

公开(公告)日：1998-12-23

申请号：GB9727213

申请日：1997-12-23

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  LUR WATER ,  SUN SHIH-WEI

IPC: H01L21/8242 ,  H01L27/108

公开(公告)号：GB2323704A

公开(公告)日：1998-09-30

申请号：GB9706081

申请日：1997-03-24

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI

IPC: H01L21/768

Abstract: A multilevel interconnect is formed on an insulating layer 30 over a semiconductor substrate 10 by forming depressions such as trenches or grooves in the surface of the insulating layer. Metal wiring lines 32 are formed by blanket depositing a layer of metal, filling the depressions on the surface of the insulating layer, and then chemical mechanical polishing the device to planarize the surface of the metal layer and the insulating layer, thereby forming a pattern of first level wiring lines. An etch stop layer 34 of a material different from the insulating layer is deposited over the first level wiring lines and over the insulating layer. A layer of dielectric material 36 different from the layer of etch stop material, is deposited over the etch stop layer. A via is formed through the layer of dielectric material and the etch stop layer is removed from within the via. Next, a glue or adhesion layer (40, Fig 10) is deposited within the via, a tungsten plug 42 formed within the via, and then a second level wiring line 46 is formed in contact with the tungsten plug.

公开(公告)号：GB2322964A

公开(公告)日：1998-09-09

申请号：GB9704722

申请日：1997-03-07

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/321 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: A thin layer of silicon nitride 26 is deposited on an oxide layer 24 and then vias are opened through the silicon nitride and silicon oxide layers to expose one of the source/drain regions 20,22 of pass transistors in a memory array. A layer of polysilicon 30 is deposited so as to extend through the vias, forming polysilicon vertical interconnects and then the layer of polysilicon is patterned to form capacitor bottom plates. A second layer of silicon oxide is deposited to cover the capacitor bottom plates and photolithography is performed to provide openings though the second silicon oxide layer to each of the capacitor bottom plates. Polysilicon is deposited to fill each of the openings and chemical mechanical polishing is performed to remove excess polysilicon using the silicon oxide layer as a polish stop. The second oxide layer is stripped to leave the capacitor bottom plates with fins or posts 36. A capacitor dielectric 38 is then formed over the capacitor bottom electrodes, and capacitor upper electrodes 40 are formed.