公开(公告)号：US6362101B2

公开(公告)日：2002-03-26

申请号：US97660597

申请日：1997-11-24

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YANG MING-SHENG ,  WU JUAN-YUAN ,  LUR WATER ,  SUN SHIH-WEI

IPC: H01L21/304 ,  C09K3/14 ,  H01L21/321 ,  H01L21/302

CPC classification number: H01L21/3212 ,  C09K3/1463

Abstract: A method for chemical mechanical polishing a component includes providing an oxide layer and forming at least one via through the oxide layer. A tungsten layer is formed within the via and over the oxide layer. A first chemical mechanical polishing step is carried out on a polishing pad using a first slurry having an oxidizing component and having a pH of approximately 2 to approximately 4 to remove the tungsten layer from over the oxide layer. A second chemical mechanical polishing step is carried out on the polishing pad using a second slurry having a pH of approximately 2 to approximately 4 to polish scratches out of the oxide layer.

Abstract translation: 用于化学机械抛光组分的方法包括提供氧化物层并通过氧化物层形成至少一个通孔。 在通孔内和氧化物层上形成钨层。 在抛光垫上使用具有氧化成分的第一浆料并且具有约2至约4的pH进行第一化学机械抛光步骤以从氧化物层上方除去钨层。 使用pH为约2〜约4的第二浆料在抛光垫上进行第二化学机械抛光步骤以抛光出氧化物层的划痕。

公开(公告)号：FR2770027B1

公开(公告)日：2001-11-09

申请号：FR9800605

申请日：1998-01-21

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI RUNG ,  LUR WATER ,  SUN SHIH WEI ,  SHIH HSUEH HAO

IPC: C23C16/04 ,  C23C16/24 ,  H01L21/02 ,  H01L21/205 ,  H01L21/285 ,  H01L21/8242 ,  H01L27/108

公开(公告)号：NL1010203C2

公开(公告)日：2000-03-30

申请号：NL1010203

申请日：1998-09-28

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  LUR WATER ,  SUN SHIH-WEI ,  HUANG YIMIN

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

Abstract: A method for forming a barrier layer comprising the steps of first providing a semiconductor substrate that has a conductive layer already formed thereon. Then, a dielectric layer such as an organic low-k dielectric layer is deposited over the conductive layer and the semiconductor substrate. Next, an opening in formed in the dielectric layer exposing the conductive layer. Thereafter, a first barrier layer is deposited into the opening and the surrounding area. The first barrier layer can be a silicon-contained layer or a doped silicon (doped-Si) layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method, a low-pressure chemical vapor deposition (LPCVD) method, an electron beam evaporation method or a sputtering method. Finally, a second barrier layer is formed over the first barrier layer. The second barrier layer can be a titanium/titanium nitride (Ti/TiN) layer, a tungsten nitride (WN) layer, a tantalum (Ta) layer or a tantalum nitride (TaN) layer.

公开(公告)号：GB2326524B

公开(公告)日：1999-11-17

申请号：GB9727213

申请日：1997-12-23

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  LUR WATER ,  SUN SHIH-WEI

IPC: H01L21/8242 ,  H01L27/108

公开(公告)号：NL1008071C2

公开(公告)日：1999-07-21

申请号：NL1008071

申请日：1998-01-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  LUR WATER ,  SUN SHIH-WEI

IPC: H01L21/8242 ,  H01L21/3205 ,  H01L21/768

Abstract: Fabricating a DRAM device comprises: (a) forming a transistor (55) with a gate (53), a source/drain region (52) and a word line (54) on a silicon substrate (50); (b) covering the transistor with an oxide layer (56); (c) forming a contact opening (57) in the oxide layer to expose a surface of the source/drain region; (d) forming a conductive layer (58) in the contact opening and covering the oxide layer; (e) patterning the conductive layer to form at least one bottom electrode (59) which is coupled with the source/drain region (52) by way of the contact opening; (f) forming a dielectric layer (60) over a surface of the bottom electrode and the oxide layer; (g) covering the dielectric layer with a titanium nitride layer to form a top electrode (61); (h) forming a titanium layer (62) on the top electrode; and (i) forming an interlevel dielectric layer (63).

公开(公告)号：GB2328078A

公开(公告)日：1999-02-10

申请号：GB9716395

申请日：1997-08-01

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LIN TONY ,  LUR WATER ,  SUN SHIH-WEI

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/08

Abstract: A method of making a MOS device comprising a self-aligned silicide layer 31 and an impurity diffusion region 29 in a lower part of the source/drain regions 23a adjacent to an isolating region 24, includes over-etching (Figure 2B) the isolating regions 24 to expose the surface of the source/drain regions. Ion implantation (Figure 2C) at a large tilt angle increases the junction depth of the source/drain regions and prevents the metallic silicide lying at the edge of the isolating region from getting too close to the source/drain junction and causing unwanted current leakages. The silicide layer can thus be formed over the exposed source/drain surfaces, resulting in more surface area for the formation of a wide border contact window 34, resulting in a lowering of both contact resistance and sheet resistance.

公开(公告)号：GB2326523A

公开(公告)日：1998-12-23

申请号：GB9726685

申请日：1997-12-17

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI ,  YANG MING-SHENG ,  WU JUAN-YUAN ,  LUR WATER

IPC: C09K3/14 ,  H01L21/321

公开(公告)号：DE19734837A1

公开(公告)日：1998-11-26

申请号：DE19734837

申请日：1997-08-12

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LIN TONY ,  LUR WATER ,  SUN SHIH-WEI

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

Abstract: The method involves, on a substrate (21), depositing a first insulation layer (25), which is anisotropically over-etched to remove the layer and to form spacing elements (26) on corresponding side walls of the gate region (23) and for simultaneous removing a part of the top layer of the insulator regions (24). Second type ions are implanted with an inclination angle into the metal-oxide-semiconductor (MOS) component region (22), using the spacing elements and gate region as a mask to form several source/drain regions (27) in the substrate on each side of the gate region. A metal film is formed on a substrate surface, the MOS component region and the spacing elements. A rapid thermal treatment results in a metal-silicide layer (31), followed by specified process steps.

公开(公告)号：FR2763424A1

公开(公告)日：1998-11-20

申请号：FR9705992

申请日：1997-05-15

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI RUNG ,  LIU MONG CHUNG ,  LUR WATER ,  SUN SHIH WEI

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522

Abstract: Making an integrated circuit with first (78) and second (76) level conductor structures comprises: (a) providing a substrate (50) with integrated circuit device(s); (b) providing an interlayer dielectric layer (52) over the substrate; (c) providing an etch stop layer (54) over it; (d) patterning the etch stop layer to define openings corresponding to positions where first level conductor structures are to be formed; (e) providing an intermetallic dielectric layer (58) over the patterned etch stop layer; (f) forming a second level mask over the intermetallic dielectric layer; this mask having openings corresponding to positions where second level conductor structures are to be formed; (g) etching through the openings in the second level mask to form second level conductor openings in the intermetallic dielectric layer; (h) etching through the openings in the patterned etch stop layer to form first level conductor openings in the interlayer dielectric layer; the edges of the openings have a tapered configuration; they provide for a step-free transition with the second level conductor openings; and (i) depositing metal into the first and second level conductor openings.

公开(公告)号：FR2758210A1

公开(公告)日：1998-07-10

申请号：FR9700024

申请日：1997-01-03

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LUR WATER ,  LIN TONY

IPC: H04B10/10 ,  H01L29/49 ,  H01L21/28

Abstract: The infrared transmitter includes a transmission device with transmitter and receiver on a computer. A second transmission device includes a transmitter and receiver on a keyboard. A transmission angle adjustment mask is arranged on the first or second transmission device to adjust the transmission angle of the device. A spherical direction adjustment device is included.