公开(公告)号：US09870996B1

公开(公告)日：2018-01-16

申请号：US15247948

申请日：2016-08-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L21/8234 ,  H01L23/535 ,  H01L27/088 ,  H01L27/02 ,  H01L21/768 ,  H01L29/423

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42356 ,  H01L29/66545

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, a plurality of gates and a plurality of plugs. The gates are disposed on the substrate and extend in a first direction. The gates include a first gate and a second gate. The first gate includes a first protruding portion extending in a second direction. The plugs are disposed parallel to one another on the substrate. The plugs include a first plug and a second plug. The first plug and the second plug cover the first gate and the second gate respectively. A central axis of the first plug is shifted from a central axis of the first gate toward the second direction, and a central axis of the second plug is shifted from a central axis of the second gate toward the second direction.

公开(公告)号：US09865593B1

公开(公告)日：2018-01-09

申请号：US15402245

申请日：2017-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Hsiang-Hung Peng ,  Wei-Hao Huang ,  Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L27/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L28/20 ,  H01L28/24

Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.

公开(公告)号：US20170287843A1

公开(公告)日：2017-10-05

申请号：US15091562

申请日：2016-04-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Ying-Cheng Liu ,  Ching-Wen Hung ,  Yi-Hui Lee ,  Chih-Sen Huang

IPC: H01L23/532 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/53266 ,  H01L21/285 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L27/092

Abstract: According to a preferred embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a substrate having a first region and a second region; a first contact plug on the first region, and a second contact plug on the second region. Preferably, the first contact plug includes a first interfacial layer having a first conductive type and a first work function metal layer having the first conductive type on the first interfacial layer, and the second contact plug includes a second interfacial layer having a second conductive type and a second work function metal layer having the second conductive type on the second interfacial layer.

公开(公告)号：US20170263597A1

公开(公告)日：2017-09-14

申请号：US15604685

申请日：2017-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Yi-Wei Chen ,  Yung-Feng Cheng ,  Li-Ping Huang ,  Chun-Hsien Huang ,  Chia-Wei Huang ,  Yu-Tse Kuo

IPC: H01L27/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/768 ,  H01L27/11 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7851

Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

公开(公告)号：US09721841B1

公开(公告)日：2017-08-01

申请号：US15140019

申请日：2016-04-27

Applicant: United Microelectronics Corp.

Inventor： Jun-Jie Wang ,  Yu-Lin Wang ,  Ching-Wen Hung ,  En-Chiuan Liou ,  Chih-Sen Huang

IPC: H01L21/82 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/088 ,  H01L29/49 ,  H01L29/06

CPC classification number: H01L21/823456 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/4916

Abstract: An electronic circuit includes a plurality of fin lines on a substrate and a plurality of gate lines with a first line width, crossing over the fin lines. The gate lines are parallel and have a plurality of discontinuous regions forming as a plurality of slots. A region of any one of the gate lines adjacent to an unbalance of the slots has a second line width smaller than the first line width.

公开(公告)号：US20170162449A1

公开(公告)日：2017-06-08

申请号：US15434067

申请日：2017-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Wei-Cyuan Lo ,  Ming-Jui Chen ,  Chia-Lin Lu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Tan-Ya Yin ,  Chia-Wei Huang ,  Shu-Ru Wang ,  Yung-Feng Cheng

IPC: H01L21/8238 ,  H01L27/11 ,  H01L23/535 ,  H01L21/768 ,  H01L27/092

CPC classification number: H01L21/823871 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

公开(公告)号：US20170084721A1

公开(公告)日：2017-03-23

申请号：US14862165

申请日：2015-09-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Shih-Fang Tzou

IPC: H01L29/66 ,  H01L21/768

CPC classification number: H01L29/66795 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66545

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a gate structure is formed on a substrate, and two source/drain regions are formed. Then, a contact etching stop layer (CESL) is formed to cover the source/drain regions, and a first interlayer dielectric (ILD) layer is formed on the CESL. Next, a replace metal gate process is performed to form a metal gate and a capping layer on the metal gate, and a second ILD layer is formed on the first ILD layer. Following these, a first opening is formed in the second and first ILD layers to partially expose the CESL, and a second opening is formed in the second ILD to expose the capping layer. Finally, the CESL and the capping layer are simultaneously removed.

公开(公告)号：US20170077257A1

公开(公告)日：2017-03-16

申请号：US14880275

申请日：2015-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/423

CPC classification number: H01L29/4966 ,  H01L29/42376

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, and an interlayer dielectric disposed on the substrate which has agate structure therein. The gate structure further includes a gate electrode with a protruding portion, and a gate dielectric layer disposed between the gate electrode and the substrate. A spacer is disposed between the interlayer dielectric and the gate electrode. An insulating cap layer is disposed atop the gate electrode and encompasses the top and the sidewall of the protruding portion.

Abstract translation: 公开了半导体结构。 半导体结构包括衬底和设置在其上具有玛瑙结构的衬底上的层间电介质。 栅极结构还包括具有突出部分的栅极电极和设置在栅极电极和衬底之间的栅极电介质层。 间隔物设置在层间电介质和栅电极之间。 绝缘盖层设置在栅极顶部并且包围突出部分的顶部和侧壁。

公开(公告)号：US20170047251A1

公开(公告)日：2017-02-16

申请号：US14824091

申请日：2015-08-12

Applicant: United Microelectronics Corp.

Inventor： Yi-Hui Lee ,  Kun-Ju Li ,  Wei-Cyuan Lo ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/768 ,  H01L21/311 ,  H01L29/78 ,  H01L21/3105

CPC classification number: H01L21/76895 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device includes: providing a semiconductor having active regions; depositing a dielectric layer on the semiconductor; forming a patterned etch mask on the dielectric layer; depositing a further dielectric layer on the dielectric layer and the patterned etch mask; planarizing the further dielectric layer until the patterned etch mask is exposed; and forming a further patterned etch mask having an opening on the further dielectric layer so that portions of the patterned etch mask are exposed from the opening.

Abstract translation: 一种制造半导体器件的方法包括：提供具有有源区的半导体; 在半导体上沉积介电层; 在介电层上形成图案化的蚀刻掩模; 在介电层和图案化的蚀刻掩模上沉积另外的介电层; 平面化另外的介电层，直到图案化的蚀刻掩模曝光; 以及形成另一图案化的蚀刻掩模，其在所述另外的电介质层上具有开口，使得所述图案化蚀刻掩模的部分从所述开口露出。

公开(公告)号：US09543211B1

公开(公告)日：2017-01-10

申请号：US14864881

申请日：2015-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Yu-Cheng Tung ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  En-Chiuan Liou ,  Wei-Hao Huang ,  Chih-Sen Huang ,  Ching-Wen Hung

IPC: H01L21/70 ,  H01L21/8234 ,  H01L21/283 ,  H01L27/088

CPC classification number: H01L21/823437 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/088

Abstract: A manufacturing method of a semiconductor structure includes the following steps. Gate structures are formed on a semiconductor substrate. A source/drain contact is formed between two adjacent gate structures. The source/drain contact is recessed by a recessing process. A top surface of the source/drain contact is lower than a top surface of the gate structure after the recessing process. A stop layer is formed on the gate structures and the source/drain contact after the recessing process. A top surface of the stop layer on the source/drain contact is lower than the top surface of the gate structure. A semiconductor structure includes the semiconductor substrate, the gate structures, a gate contact structure, and the source/drain contact. The source/drain contact is disposed between two adjacent gate structures, and the top surface of the source/drain contact is lower than the top surface of the gate structure.

Abstract translation: 半导体结构的制造方法包括以下步骤。 栅极结构形成在半导体衬底上。 在两个相邻栅极结构之间形成源极/漏极接触。 源极/漏极接触器通过凹陷工艺凹陷。 源极/漏极接触件的顶表面在凹陷过程之后低于栅极结构的顶表面。 在凹陷过程之后，在栅极结构和源极/漏极触点上形成阻挡层。 源极/漏极接触点上的阻挡层的顶表面低于栅极结构的顶表面。 半导体结构包括半导体衬底，栅极结构，栅极接触结构和源极/漏极接触。 源极/漏极触点设置在两个相邻的栅极结构之间，源极/漏极接触的顶表面低于栅极结构的顶部表面。