中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

130 records (took 0.026 seconds)

    SEMICONDUCTOR DEVICE AND A FABRICATION METHOD THEREOF
    91.
    发明申请
    SEMICONDUCTOR DEVICE AND A FABRICATION METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20170047422A1

    公开(公告)日：2017-02-16

    申请号：US14855357

    申请日：2015-09-15

    Applicant: United Microelectronics Corp.

    Inventor： Chien-Ting Lin ,  Shih-Fang Tzou

    IPC: H01L29/66 ,  H01L23/535 ,  H01L21/768 ,  H01L29/78

    CPC classification number: H01L29/6656 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: A semiconductor device includes a substrate, gate electrodes, spacers and contact structures. The gate electrodes are disposed on the substrate, and the spacers are disposed on the sidewalls of the gate electrodes. Each of the spacers has an inner sidewall and an outer sidewall. The contact structure is disposed between the gate electrodes, and its bottom is in direct contact with all the region of the outer sidewall of the spacers.

    Abstract translation: 半导体器件包括衬底，栅电极，间隔物和接触结构。 栅电极设置在衬底上，并且间隔物设置在栅电极的侧壁上。 每个间隔件具有内侧壁和外侧壁。 接触结构设置在栅电极之间，其底部与间隔物的外侧壁的所有区域直接接触。

    Metal gate structure
    92.
    发明授权
    Metal gate structure 有权
    金属门结构

    公开(公告)号：US09263540B1

    公开(公告)日：2016-02-16

    申请号：US14852624

    申请日：2015-09-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Yi-Wei Chen ,  Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Hsiao-Pang Chou ,  Chia-Lin Lu

    IPC: H01L27/088 ,  H01L29/49 ,  H01L29/423

    CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/66545

    Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.

    Abstract translation: 金属栅极结构至少包括衬底，电介质层，第一和第二沟槽，第一金属层和第二金属层以及两个盖层。 特别地，介电层设置在基板上，并且第一和第二沟槽设置在电介质层中。 第一沟槽的宽度小于第二沟槽的宽度。 第一和第二金属层分别设置在第一沟槽和第二沟槽中，第一金属层的高度小于或等于第二金属层的高度。 盖层分别设置在第一金属层的顶表面和第二金属层的顶表面中。

    Method for generating layout pattern
    94.
    发明授权
    Method for generating layout pattern 有权
    生成布局模式的方法

    公开(公告)号：US09208276B1

    公开(公告)日：2015-12-08

    申请号：US14822907

    申请日：2015-08-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Chao Tsao ,  Shih-Fang Hong ,  Chia-Wei Huang ,  Ming-Jui Chen ,  Shih-Fang Tzou ,  Ming-Te Wei

    IPC: G06F17/50 ,  G03F1/36

    CPC classification number: G06F17/5068 ,  G03F1/144 ,  G03F1/36

    Abstract: A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask.

    Abstract translation: 生成包括FinFET结构布局的布局图案的方法包括以下处理。 首先，将包括具有简单整数比例的间距的子图案的布局图案提供给计算机系统。 然后将子图案分类为第一子图案和第二子图案。 之后，产生第一条纹图案和至少一个第二条纹图案。 第一条形图案的纵向边缘与第一子图案的纵向边缘对准，并且第一条纹图案具有相等的间距和宽度。 第二条纹图案的位置对应于空白图案的位置，第二条纹图案的间距或宽度不同于第一条纹图案的间距或宽度。 最后，将第一条纹图案和第二条纹图案输出到光掩模。

    Metal gate transistor
    95.
    发明授权
    Metal gate transistor 有权
    金属栅晶体管

    公开(公告)号：US09196546B2

    公开(公告)日：2015-11-24

    申请号：US14025833

    申请日：2013-09-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

    IPC: H01L29/76 ,  H01L21/8238

    CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

    Abstract: A metal gate transistor is disclosed. The metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate. The metal gate further includes a high-k dielectric layer, a bottom barrier metal (BBM) layer on the high-k dielectric layer, a first work function layer on the BBM layer, a second work function layer between the BBM layer and the first work function layer, and a low resistance metal layer on the first work function layer. Preferably, the first work function layer includes a p-type work function layer and the second work function layer includes a n-type work function layer.

    Abstract translation: 公开了一种金属栅极晶体管。 金属栅极晶体管包括衬底，衬底上的金属栅极和衬底中的源极/漏极区域。 金属栅极还包括高k电介质层，高k电介质层上的底部阻挡金属（BBM）层，BBM层上的第一功函数层，BBM层和第一层之间的第二功函数层 功函数层，第一功函数层上的低电阻金属层。 优选地，第一功函数层包括p型功函数层，第二功函数层包括n型功函数层。

    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH PATERNED HARD MASK
    97.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH PATERNED HARD MASK 有权
    用硬化掩模制作半导体器件的方法

    公开(公告)号：US20150179457A1

    公开(公告)日：2015-06-25

    申请号：US14639134

    申请日：2015-03-05

    Applicant: United Microelectronics Corp.

    Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Shih-Fang Tzou

    IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/311 ,  H01L29/66

    CPC classification number: H01L21/28079 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for fabricating a semiconductor device includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, and a bottom surface of the patterned mask layer is level with a top surface of the first interlayer dielectric. A spacer is then formed on each sidewall of the gate electrode. Subsequently, a second interlayer dielectric is formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.

    Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，在基板上形成第一层间电介质。 然后，在基板上形成栅电极，使得栅电极的周围被第一层间电介质包围。 之后，在栅电极上形成图案化掩模层，并且图案化掩模层的底表面与第一层间电介质的顶表面平齐。 然后在栅电极的每个侧壁上形成间隔物。 随后，形成第二层间电介质以覆盖图案化掩模层的顶表面和每个侧表面。 最后，在第一层间电介质和第二层间电介质中形成自对准接触结构。

Patent Agency Ranking