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    Method for forming semiconductor device
    92.
    发明授权
    Method for forming semiconductor device 有权
    半导体器件形成方法

    公开(公告)号：US09564371B2

    公开(公告)日：2017-02-07

    申请号：US14514374

    申请日：2014-10-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Wen Hung ,  Tsung-Hung Chang ,  Jia-Rong Wu ,  Ching-Ling Lin ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen

    IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/311

    CPC classification number: H01L21/823475 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823431

    Abstract: A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure, next, a hard mask layer and a first photoresist layer are formed on the fin structure, an first etching process is then performed on the first photoresist layer, afterwards, a plurality of patterned photoresist layers are formed on the remaining first photoresist layer and the remaining hard mask layer, where each patterned photoresist layer is disposed right above each gate structure, and the width of each patterned photoresist is larger than the width of each gate structure, and the patterned photoresist layer is used as a hard mask to perform an second etching process to form a plurality of second trenches.

    Abstract translation: 一种半导体器件的制造方法，其特征在于，首先，在基板上形成有基板，在所述散热片结构上形成有多个栅极结构，然后将硬掩模层和第一光致抗蚀剂层 形成在鳍结构上，然后在第一光致抗蚀剂层上进行第一蚀刻工艺，然后在剩余的第一光致抗蚀剂层和剩余的硬掩模层上形成多个图案化的光致抗蚀剂层，其中每个图案化的光致抗蚀剂层被设置 每个栅极结构的正上方，并且每个图案化的光致抗蚀剂的宽度大于每个栅极结构的宽度，并且图案化的光致抗蚀剂层用作硬掩模以执行第二蚀刻工艺以形成多个第二沟槽。

    Semiconductor Structure
    94.
    发明申请
    Semiconductor Structure 有权
    半导体结构

    公开(公告)号：US20160163797A1

    公开(公告)日：2016-06-09

    申请号：US14594159

    申请日：2015-01-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jiun Shen ,  Chia-Jong Liu ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Man-Ling Lu ,  Yi-Wei Chen ,  Jhen-Cyuan Li

    IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78

    CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847

    Abstract: The present invention provides a semiconductor structure, comprising a substrate, a gate structure, a source/drain region and at least a dislocation. The gate structure is disposed on the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure. The dislocation is located in the source/drain region, and is asymmetrical relating to a middle axis of the source/drain region.

    Abstract translation: 本发明提供一种半导体结构，其包括衬底，栅极结构，源极/漏极区域和至少位错。 栅极结构设置在基板上。 源极/漏极区域在栅极结构的两侧设置在衬底中。 位错位于源极/漏极区域中，并且与源极/漏极区域的中间轴线不对称。

    FABRICATION METHOD OF SEMICONDUCTOR STRUCTURE
    98.
    发明申请
    FABRICATION METHOD OF SEMICONDUCTOR STRUCTURE 有权
    半导体结构的制造方法

    公开(公告)号：US20150364568A1

    公开(公告)日：2015-12-17

    申请号：US14341838

    申请日：2014-07-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Man-Ling Lu ,  Chia-Jong Liu ,  Wen-Jiun Shen ,  Yi-Wei Chen

    IPC: H01L29/66

    CPC classification number: H01L29/6656 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

    Abstract: A fabrication method of a semiconductor structure includes the following steps. First of all, a gate structure is provided on a substrate, and a first material layer is formed on the substrate and the gate structure. Next, boron dopant is implanted to the substrate, at two sides of the gate structure, to form a first doped region, and P type conductive dopant is implanted to the substrate, at the two sides of the gate structure, to form a second doped region. As following, a second material layer is formed on the first material layer. Finally, the second material layer, the first material layer and the substrate at the two sides of the gate structure are etched sequentially, and a recess is formed in the substrate, at the two sides of the gate structure, wherein the recess is positioned within the first doped region.

    Abstract translation: 半导体结构的制造方法包括以下步骤。 首先，在基板上设置栅极结构，在基板和栅极结构上形成第一材料层。 接下来，在栅极结构的两侧将硼掺杂剂注入到衬底中以形成第一掺杂区，并且在栅极结构的两侧将P型导电掺杂剂注入到衬底中，以形成第二掺杂区 地区。 如下，在第一材料层上形成第二材料层。 最后，栅极结构的两侧的第二材料层，第一材料层和衬底被顺序地蚀刻，并且在栅极结构的两侧在衬底中形成凹部，其中凹部位于 第一掺杂区域。

    SEMICONDUCTOR STRUCTURE HAVING A METAL GATE WITH SIDE WALL SPACERS
    99.
    发明申请
    SEMICONDUCTOR STRUCTURE HAVING A METAL GATE WITH SIDE WALL SPACERS 有权
    具有侧壁间隔的金属门的半导体结构

    公开(公告)号：US20150249142A1

    公开(公告)日：2015-09-03

    申请号：US14698828

    申请日：2015-04-28

    Applicant: United Microelectronics Corp.

    Inventor： Yi-Wei Chen ,  Nien-Ting Ho ,  Chien-Chung Huang ,  Chin-Fu Lin

    IPC: H01L29/66 ,  H01L21/263 ,  H01L29/40

    CPC classification number: H01L29/4983 ,  H01L21/2633 ,  H01L21/28026 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/7833

    Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.

    Abstract translation: 一种形成具有金属栅极的半导体结构的方法。 首先，提供半导体衬底。 随后，至少在半导体衬底上形成栅极结构。 之后，形成围绕栅结构的间隔结构。 然后，形成层间电介质。 之后，对层间电介质进行平面化处理。 然后，去除牺牲层的一部分以形成初始蚀刻深度，使得形成开口以露出间隔物结构的一部分。 暴露于开口的间隔结构的部分被去除以扩大开口。 之后，通过开口完全除去牺牲层。 最后，形成栅极导电层以填充开口。

    Method of fabricating a MOS device using a stress-generating material
    100.
    发明授权
    Method of fabricating a MOS device using a stress-generating material 有权
    使用应力产生材料制造MOS器件的方法

    公开(公告)号：US09105651B2

    公开(公告)日：2015-08-11

    申请号：US13940103

    申请日：2013-07-11

    Applicant: United Microelectronics Corp.

    Inventor： Tsung-Hung Chang ,  Yi-Wei Chen ,  I-Fang Huang

    IPC: H01L21/00 ,  H01L29/66

    CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823468 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

    Abstract: Provided is a method of fabricating a MOS device including the following steps. A gate structure is formed on a substrate and a first spacer is formed at a sidewall of the gate structure. A first implant process is performed to form source and drain extension regions in the substrate. A spacer material layer is formed on the gate structure, the first spacer and the substrate. A treatment process is performed so that stress from the spacer material layer is applied onto and memorized in a channel between two source and drain extension regions. An anisotropic process is performed to remove a portion of the spacer material so that a second spacer is formed. A second implant process is performed to form source and drain regions in the substrate.

    Abstract translation: 提供了一种制造MOS器件的方法，包括以下步骤。 栅极结构形成在衬底上，并且第一间隔物形成在栅极结构的侧壁处。 执行第一注入工艺以在衬底中形成源极和漏极延伸区域。 在栅极结构，第一间隔物和衬底上形成间隔物层。 执行处理过程，使得来自间隔物材料层的应力施加到并存储在两个源极和漏极延伸区域之间的沟道中。 执行各向异性处理以去除间隔物材料的一部分，从而形成第二间隔物。 执行第二注入工艺以在衬底中形成源区和漏区。

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