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    Method for producing integrated microsystems
    91.
    发明申请
    Method for producing integrated microsystems 失效
    集成微系统的制作方法

    公开(公告)号：US20040127008A1

    公开(公告)日：2004-07-01

    申请号：US10613459

    申请日：2003-07-03

    Inventor： Wilhelm Frey ,  Franz Laermer ,  Christoph Duenn

    IPC: H01L021/28

    CPC classification number: B81C1/00571 ,  B81C1/00595 ,  B81C2201/0133 ,  B81C2201/016 ,  B81C2203/0735 ,  C23F1/14 ,  H01L21/30604

    Abstract: A method for producing a microsystem that has, situated on a substrate, a first functional layer that includes a conductive area and a sublayer. Situated on the first functional layer is a second mechanical functional layer, which is first initially applied onto a sacrificial layer situated and structured on the first functional layer. In addition, a layer is situated on the side of the sublayer facing away from the conductive area. The layer constitutes a protective layer on the first functional layer that acts in areas during a sacrificial layer etching process so that during removal of the sacrificial layer no etching of the areas of the first functional layer covered by the protective layer occurs, and that in the region of the areas of the first functional layer implemented without the protective layer the sublayer is removed essentially selectively to the conductive area at the same time as the sacrificial layer. Further, a method is described for producing integrated microsystems having silicon-germanium functional layers, sacrificial layers containing germanium, and open metal surfaces. The sacrificial layers containing germanium are at least partially removed in an etching solution, a pH value of the etching solution being kept at least approximately neutral during the etching procedure using a buffer.

    Abstract translation: 一种微系统的制造方法，其具有位于基板上的包括导电区域和子层的第一功能层。 位于第一功能层上的是第二机械功能层，其首先被初始施加到位于第一功能层上并构成的牺牲层上。 此外，层位于子层背离导电区域的一侧。 该层在第一功能层上构成保护层，其在牺牲层蚀刻工艺期间在区域中起作用，使得在去除牺牲层期间不会发生由保护层覆盖的第一功能层的区域的蚀刻， 在没有保护层的情况下实现的第一功能层的区域的区域在与牺牲层同时基本上选择性地去除导电区域。 此外，描述了一种用于制造具有硅 - 锗功能层，包含锗的牺牲层和开放金属表面的集成微系统的方法。 在蚀刻溶液中至少部分地除去含有锗的牺牲层，在使用缓冲液的蚀刻过程中，蚀刻溶液的pH值保持至少大致为中性。

    Integrated driver process flow
    92.
    发明申请
    Integrated driver process flow 有权
    集成驱动程序流程

    公开(公告)号：US20040109215A1

    公开(公告)日：2004-06-10

    申请号：US10703827

    申请日：2003-11-07

    Inventor： James A. Hunter

    IPC: H01L021/00 ,  G02F001/00 ,  G02B026/00 ,  G02F001/03

    CPC classification number: G02B26/0808 ,  B81B2201/045 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/016 ,  B81C2203/0735 ,  B81C2203/0778 ,  H01L27/0611

    Abstract: An integrated device including one or more device drivers and a diffractive light modulator monolithically coupled to the one or more driver circuits. The one or more driver circuits are configured to process received control signals and to transmit the processed control signals to the diffractive light modulator. A method of fabricating the integrated device preferably comprises fabricating a front-end portion for each of a plurality of transistors, isolating the front-end portions of the plurality of transistors, fabricating a front-end portion of a diffractive light modulator, isolating the front end portion of the diffractive light modulator, fabricating interconnects for the plurality of transistors, applying an open array mask and wet etch to access the diffractive light modulator, and fabricating a back-end portion of the diffractive light modulator, thereby monolithically coupling the diffractive light modulator and the plurality of transistors.

    Abstract translation: 包括一个或多个器件驱动器和单片耦合到所述一个或多个驱动器电路的衍射光调制器的集成器件。 一个或多个驱动器电路被配置为处理接收到的控制信号并将经处理的控制信号传送到衍射光调制器。 一种制造集成器件的方法优选包括制造用于多个晶体管中的每一个晶体管的前端部分，隔离多个晶体管的前端部分，制造衍射光调制器的前端部分，将前部 衍射光调制器的端部，制造用于多个晶体管的互连，施加开放阵列掩模和湿蚀刻以访问衍射光调制器，以及制造衍射光调制器的后端部分，从而将衍射光 调制器和多个晶体管。

    Integrated driver process flow
    93.
    发明申请
    Integrated driver process flow 有权
    集成驱动程序流程

    公开(公告)号：US20040106221A1

    公开(公告)日：2004-06-03

    申请号：US10720498

    申请日：2003-11-24

    Inventor： James A. Hunter ,  Charles B. Roxlo ,  Alexander Payne

    IPC: H01L021/00

    CPC classification number: G02B26/0808 ,  B81B2201/045 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/016 ,  B81C2203/0735 ,  B81C2203/0778 ,  H01L27/0611

    Abstract: An integrated device includes one or more device drivers and a micro-electro-mechanical system (MEMS) structure monolithically coupled to the one or more device drivers. The one or more device drivers are configured to process received control signals and to transmit the processed control signals to the MEMS structure. Methods of fabricating integrated devices are also disclosed.

    Abstract translation: 集成器件包括一个或多个器件驱动器和与该一个或多个器件驱动器单片耦合的微机电系统（MEMS）结构。 一个或多个设备驱动器被配置为处理接收的控制信号并将经处理的控制信号传送到MEMS结构。 还公开了制造集成器件的方法。

    High density wafer production method
    95.
    发明申请
    High density wafer production method 失效
    高密度晶圆生产方法

    公开(公告)号：US20020123232A1

    公开(公告)日：2002-09-05

    申请号：US09683692

    申请日：2002-02-04

    Inventor： Tsung-Ping Hsu ,  In-Yao Lee ,  Hung-Sheng Hu ,  Chung-Cheng Chou ,  Wei-Lin Chen

    IPC: H01L021/302 ,  H01L021/461

    CPC classification number: B81C1/00626 ,  B81C2201/0133 ,  B81C2201/016

    Abstract: A gradational etching method for high density wafer production. The gradational etching method acts on a substrate having a first passivation layerand a second passivation layer on a top surface and a bottom surface, respectively, of the substrate. A first etching process is performed to simultaneously etch the substrate and the first passivation layer to remove the first passivation layer. Finally, a second etching process is performed to etch the substrate to a designated depth that is used to control the thickness of the wafer after the second etching process.

    Abstract translation: 用于高密度晶片生产的渐变蚀刻方法。 分级蚀刻方法分别作用于具有基板的顶表面和底表面上的第一钝化层和第二钝化层的基板上。 执行第一蚀刻工艺以同时蚀刻衬底和第一钝化层以去除第一钝化层。 最后，执行第二蚀刻工艺以将衬底蚀刻到用于在第二蚀刻工艺之后控制晶片的厚度的指定深度。

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