公开(公告)号：KR1020040006128A

公开(公告)日：2004-01-24

申请号：KR1020020039664

申请日：2002-07-09

Applicant: 주식회사 티엘아이

Inventor： 이승훈 ,  문정웅

IPC: H03M1/12

CPC classification number: H03M1/1245 ,  H03M1/361 ,  H03M2201/62 ,  H03M2201/932

Abstract: PURPOSE: A subranging analog-to-digital converter is provided to reduce the number of switches and supplying lines to half by only one MUX, thereby reducing the overall layout area by 20%. CONSTITUTION: A subranging analog-to-digital converter(ADC) includes a sample holder(205), a reference voltage generator(210), an upper comparator(220), an upper encoder(270), an absolute value selection logic unit(230), a MUX(240), a lower comparator(260) and a lower encoder(280). The subranging ADC converts an analog signal inputted from outside into a digital signal having a predetermined number of bits. Each of the comparators in the lower comparator(260) compares the sampling voltage difference with one selected among the lower reference voltage difference and the complementary lower reference voltage difference having a sign opposite to the lower reference voltage difference.

Abstract translation: 目的：提供一个子系统模数转换器，以减少交换机的数量，并将线路提供给只有一个MUX的一半，从而将总体布局面积减少20％。 构成：子阵列模数转换器（ADC）包括一个样本保持器（205），一个参考电压发生器（210），一个上部比较器（220），一个上部编码器（270），一个绝对值选择逻辑单元 230），MUX（240），下比较器（260）和下编码器（280）。 子范围ADC将从外部输入的模拟信号转换成具有预定位数的数字信号。 下比较器（260）中的每个比较器将采样电压差与下参考电压差和具有与较低参考电压差相反的符号的互补下参考电压差中选择的一个进行比较。

公开(公告)号：KR1020020072627A

公开(公告)日：2002-09-18

申请号：KR1020010012545

申请日：2001-03-12

Applicant: 학교법인 정석인하학원

Inventor： 윤광섭 ,  정진원

IPC: H03M1/12

CPC classification number: H03M1/141 ,  H03M2201/62 ,  H03M2201/814

Abstract: PURPOSE: A current-driven folding/interpolating analog/digital converter is provided, which has a small chip area and a low power consumption and has a fast signal processing speed. CONSTITUTION: A reference voltage generation part(10) generates a reference voltage to compare with an analog input of a folding amplification stage. An arithmetic folding part(20) has a plurality of arithmetic folding blocks outputting a pair of positive and negative waveforms by preprocessing a sinusoidal folding signal having multi cross points by receiving an input signal. A current-driven interpolating circuit(30) outputs folding signals having cross points of additional equivalent gap from the folding signal generated from two random adjacent arithmetic folding blocks of the arithmetic folding part. A current comparator part(40) converts a plurality of full differential folding current signals obtained from the interpolating circuit into a plurality of circular codes. And a digital encoder part(50) converts the plurality of circular codes from the current comparator part into encoded digital signals.

Abstract translation: 目的：提供电流驱动的折叠/内插模拟/数字转换器，具有小的芯片面积和低功耗，并具有快速的信号处理速度。 构成：参考电压产生部分（10）产生参考电压以与折叠放大级的模拟输入进行比较。 算术折叠部分（20）具有通过接收输入信号预处理具有多个交叉点的正弦折叠信号而输出一对正和负波形的多个算术折叠块。 电流驱动内插电路（30）从由算术折叠部分的两个随机相邻算术折叠块产生的折叠信号输出具有额外等效间隙的交叉点的折叠信号。 电流比较器部分（40）将从内插电路获得的多个全差分折叠电流信号转换为多个循环码。 并且数字编码器部分（50）将来自当前比较器部分的多个圆形码转换成编码的数字信号。

公开(公告)号：KR1020000074467A

公开(公告)日：2000-12-15

申请号：KR1019990018439

申请日：1999-05-21

Applicant: 에스케이하이닉스 주식회사

Inventor： 김병두

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M2201/194 ,  H03M2201/61 ,  H03M2201/62 ,  H03M2201/8132 ,  H03M2201/932

Abstract: PURPOSE: A digital-analog converter used for an LCD driver is provided to minimize time delay and line resistance of data signal lines to improve the efficiency of a system. CONSTITUTION: A digital-analog converter used for an LCD driver includes a controller(100) for receiving data signals(D0,D1) to generate control signals(C1-C4), a controller(110) for receiving data signals(D2,D3) to generate control signals(C5-C8), an inverter(120) for inverting the eight control signals, and a selector(130) for receiving high power supply voltages(VH0-VH15) having different voltage levels to selectively output them according to the fifth to eighth control signals. The digital-analog converter also includes a selector(140) for power supply voltages(VL0-VL15) having different voltage levels to selectively output them according to the first to fourth control signals, and a selector(150) for accepting the output signals of the two selectors to selectively output them as output signals(POUT,NOUT) according to the output signal of the inverter.

Abstract translation: 目的：提供用于LCD驱动器的数模转换器，以最小化数据信号线的延时和线路电阻，从而提高系统的效率。 构成：用于LCD驱动器的数模转换器包括用于接收数据信号（D0，D1）以产生控制信号（C1-C4）的控制器（100），用于接收数据信号（D2，D3）的控制器 ）产生控制信号（C5-C8），用于反转八个控制信号的反相器（120），以及用于接收具有不同电压电平的高电源电压（VH0-VH15）的选择器（130），以根据 第五到第八控制信号。 数模转换器还包括用于具有不同电压电平的电源电压（VL0-VL15）的选择器（140），以根据第一至第四控制信号选择性地输出它们;以及选择器（150），用于接收 两个选择器根据变频器的输出信号选择性地输出它们作为输出信号（POUT，NOUT）。

公开(公告)号：KR1020000050404A

公开(公告)日：2000-08-05

申请号：KR1019990000265

申请日：1999-01-08

Applicant: 삼성전자주식회사

Inventor： 백승범

IPC: H03M1/66 ,  H03M1/74

CPC classification number: H03M1/70 ,  H03M2201/62 ,  H03M2201/814

Abstract: PURPOSE: A digital analog converter is provided to increasing an output range from a ground voltage to a voltage source level by constructing a DAC current source circuit using first and second current source circuits. CONSTITUTION: A bias circuit(100) generates first to fourth bias voltages of the same level. A first current source circuit(260) generates a first output voltage in response to the first and second bias voltage and first and second clock signals. A second current source circuit(270) generates a second output voltage in response to the third and fourth bias voltages and third and fourth clock signals. A decoding logic unit(210) generates the first to fourth clock signals and an output selection signal for selecting an output voltage when digital data to be converted is inputted.

Abstract translation: 目的：提供数字模拟转换器，通过使用第一和第二电流源电路构造DAC电流源电路来增加从地电压到电压源电平的输出范围。 构成：偏置电路（100）产生相同电平的第一至第四偏置电压。 第一电流源电路（260）响应于第一和第二偏置电压以及第一和第二时钟信号产生第一输出电压。 第二电流源电路（270）响应于第三和第四偏置电压以及第三和第四时钟信号产生第二输出电压。 解码逻辑单元（210）产生第一至第四时钟信号和用于在输入要转换的数字数据时选择输出电压的输出选择信号。