公开(公告)号：KR1020160002433A

公开(公告)日：2016-01-08

申请号：KR1020140080452

申请日：2014-06-30

Applicant: 엘지디스플레이 주식회사

Inventor： 김창균 ,  송홍성 ,  정태영

IPC: G09G3/20 ,  H03M1/66

CPC classification number: H03M1/66 ,  G02F1/133 ,  G09G3/20 ,  G09G5/006 ,  H03M2201/61 ,  H03M2201/814 ,  H03M2201/932

Abstract: 본발명은비디오데이터를저장하는저장레지스터와, 기준감마전압을기준으로정해진극성반전방식에따라비디오데이터를아날로그전압으로변환하는디지털아날로그컨버터와, 아날로그전압을출력신호로서출력하는출력버퍼를포함하고, 디지털아날로그컨버터는, 포지티브(Positive) 구동을위한 2가지극형의트랜지스터를포함하는포지티브디지털아날로그컨버터와, 네거티브(Negative) 구동을위한 2가지극형의트랜지스터를포함하는네거티브디지털아날로그컨버터를포함하는데이터구동집적회로와이를포함하는표시장치에관한것이다.

Abstract translation: 数据驱动集成电路及其显示装置技术领域本发明涉及数据驱动集成电路及包括该电路的显示装置。 数据驱动集成电路包括：用于存储视频数据的存储寄存器; 数模转换器，其根据相对于参考伽马电压确定的极性反转方案将视频数据转换为模拟电压; 以及用于输出模拟电压作为输出信号的输出缓冲器。 数模转换器包括一个正数字模拟转换器，包括用于正驱动的双极晶体管，以及包括用于负驱动的双极晶体管的负数模转换器。

公开(公告)号：KR1020100084746A

公开(公告)日：2010-07-28

申请号：KR1020090004052

申请日：2009-01-19

Applicant: 한국과학기술원

Inventor： 유회준 ,  김빈희

IPC: H03M1/12 ,  H03M1/66

CPC classification number: H03M1/1245 ,  H03M1/403 ,  H03M1/66 ,  H03M2201/2291 ,  H03M2201/61 ,  H03M2201/8152

Abstract: PURPOSE: A SAR analog to digital converter and conversion method can diminish the switching energy and total capacitor size by offering the sampling value to the bi node of comparator to the respective other equation. CONSTITUTION: It is input the analog input signal and the capacitor array part(100) samples the analog input voltage, the reference voltage and difference voltage of the analog input voltage. The capacitor array part stores the analog input voltage. It is input the analog input voltage and the sampled difference voltage in the respective first input node and the second input shift and the comparison unit compares the analog input voltage and difference voltage.

Abstract translation: 目的：SAR模数转换器和转换方法可以通过将比较器的双节点的采样值提供给相应的其他等式来减小开关能量和总电容大小。 构成：输入模拟输入信号，电容阵列部分（100）对模拟输入电压，模拟输入电压的参考电压和差分电压进行采样。 电容器阵列部分存储模拟输入电压。 在相应的第一输入节点和第二输入移位中输入模拟输入电压和采样的差分电压，比较单元比较模拟输入电压和差分电压。

公开(公告)号：KR1020100041364A

公开(公告)日：2010-04-22

申请号：KR1020080100513

申请日：2008-10-14

Applicant: 엘지이노텍 주식회사

Inventor： 박청용

IPC: H03M1/66

CPC classification number: H03M1/362 ,  H03M2201/61 ,  H03M2201/64 ,  H03M2201/814

Abstract: PURPOSE: An A/D converter is provided to improve the distortion of a signal by using a transmission gate switch and reducing an offset voltage. CONSTITUTION: A reference voltage generating part(10) respectively outputs a plurality of reference voltage signals which are generated at a resistor string with a plurality of resistor. A plurality of transmission gate switches(40) receives each reference voltage signal from the reference voltage generating part. The transmission gate switch maintains the state of the reference voltage signal without the offset voltage change. A plurality of comparators(20) respectively outputs 0 or 1 by comparing the input signal of the unit pixel and a reference voltage signal. An encoding unit(30) outputs the digital signal of N bit by encoding the output from the comparator.

Abstract translation: 目的：提供A / D转换器，通过使用传输门极开关并降低偏移电压来改善信号的失真。 构成：参考电压产生部分（10）分别输出在电阻器串上产生的多个参考电压信号与多个电阻器。 多个传输门开关（40）从参考电压产生部分接收每个参考电压信号。 传输门开关保持参考电压信号的状态，而不会发生偏移电压变化。 多个比较器（20）通过比较单位像素的输入信号和参考电压信号分别输出0或1。 编码单元（30）通过对比较器的输出进行编码来输出N位的数字信号。

公开(公告)号：KR1020090061416A

公开(公告)日：2009-06-16

申请号：KR1020070128423

申请日：2007-12-11

Applicant: 한국전자통신연구원

Inventor： 박봉혁 ,  이승식 ,  최상성 ,  구자현 ,  김석기

IPC: H03M1/12

CPC classification number: H03M1/0617 ,  H03M1/123 ,  H03M1/362 ,  H03M2201/11 ,  H03M2201/2216 ,  H03M2201/61 ,  H03M2201/622

Abstract: An apparatus and a method for converting flash analog to digital are provided to reduce a data error generated at a high speed operation by increasing a window of an output signal of a plurality of preambles. A flash analog-to-digital converter(100) includes a reference voltage generator(110), a reference clock generator, an amplifier, a latch unit, a signal processor(150), a bubble error remover, and an encoder(170). The reference voltage generator generates the plurality of reference voltages. The plurality of pre-amps amplify and output the difference between an analog input signal and the plurality of reference voltages. The signal processor includes a plurality of window expansion units. The plurality of window expansion units increase the window of the output signal of the plurality of pre-amps as much as the predetermined size and output the increased window. The encoder encodes the output signal of the plurality of window expansion unit and outputs the digital signal.

Abstract translation: 提供了一种用于将闪存模拟转换为数字的装置和方法，用于通过增加多个前导码的输出信号的窗口来减少在高速操作时产生的数据错误。 闪存模数转换器（100）包括参考电压发生器（110），参考时钟发生器，放大器，锁存单元，信号处理器（150），气泡误差去除器和编码器（170） 。 参考电压发生器产生多个参考电压。 多个前置放大器放大并输出模拟输入信号与多个参考电压之间的差值。 信号处理器包括多个窗口扩展单元。 多个窗口扩展单元将多个前置放大器的输出信号的窗口增加到预定大小并输出增加的窗口。 编码器对多个窗口扩展单元的输出信号进行编码，并输出数字信号。

公开(公告)号：KR1020080004807A

公开(公告)日：2008-01-10

申请号：KR1020060063579

申请日：2006-07-06

Applicant: 한국과학기술원

Inventor： 조규형 ,  전용준 ,  손영석 ,  전진용 ,  이건호

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M2201/61 ,  H03M2201/62 ,  H03M2201/81

Abstract: A current supply circuit and a digital analog converter provided with the same are provided to prevent the distortion of an output current caused by changes or ununiformity in a semiconductor process. A current supply circuit includes a corrector(310) and a current source unit(320). The corrector(310) includes a reference current source(ISRC1) and a reference current generator(3010). The reference current generator receives the reference current source to generate reference current. The current source part includes a first switch(SW1), a correction current generator(3020), a second switch(SW2), and a buffer(3000). The first switch is electrically connected with one of the reference current source and an output terminal. The correction current generator generates corrected current in accordance with the reference current generator. The second switch electrically connects the reference current generator and the correction current generator. The buffer is electrically connected between the first switch and the correction current generator.

Abstract translation: 提供电流供给电路和设置有电流供给电路的数字模拟转换器，以防止由半导体工艺中的变化或不均匀性引起的输出电流的失真。 电流源电路包括校正器（310）和电流源单元（320）。 校正器（310）包括参考电流源（ISRC1）和参考电流发生器（3010）。 参考电流发生器接收参考电流源以产生参考电流。 电流源部分包括第一开关（SW1），校正电流发生器（3020），第二开关（SW2）和缓冲器（3000）。 第一开关与参考电流源和输出端之一电连接。 校正电流发生器根据参考电流发生器产生校正电流。 第二开关电连接参考电流发生器和校正电流发生器。 缓冲器电连接在第一开关和校正电流发生器之间。

公开(公告)号：KR1020060099018A

公开(公告)日：2006-09-19

申请号：KR1020050019990

申请日：2005-03-10

Applicant: 엘지전자 주식회사

Inventor： 이우열

IPC: H03M1/66 ,  H03F3/45

CPC classification number: H03M1/1245 ,  G02F1/133 ,  H03F3/45 ,  H03M2201/61 ,  H03M2201/625 ,  H03M2201/932

Abstract: 본 발명은 아날로그 그래픽 신호를 샘플링 및 홀딩하여 증폭하는 샘플링/홀딩용 증폭기로 12비트 이상의 고해상도와, 100㎒ 이상의 고속 동작을 만족한다.
12비트 이상의 높은 해상도를 얻기 위하여 2단 증폭기로 아날로그 그래픽 신호를 2단 증폭하고, 아날로그 그래픽 신호를 2단 증폭하면서 높은 이득을 얻을 수 있도록 부스팅용 증폭기를 구비하여 이득을 증가시키고, 100㎒ 이상의 고속으로 동작할 수 있도록 하는 것으로서 제 1 바이어스 전압에 따라 소정 레벨의 정전류가 흐르는 제 1 정전류원과, 상기 정전류원에 의해 정전류가 흐르면서 입력단자로 입력되는 아날로그 그래픽 신호를 차동 증폭하는 제 1 증폭기와, 상기 차동 증폭기의 출력신호를 증폭하여 출력단자로 출력하는 제 2 증폭기와, 상기 제 2 증폭기의 증폭이득을 증가시키는 제 1 및 제 2 부스팅용 증폭기로 구성하여 고화질과, 콘트라스트 및 밝기가 향상된다.
아날로그/디지털 변환기, 샘플링/홀딩용 증폭기, 고해상도, 모니터

公开(公告)号：KR1020000003449A

公开(公告)日：2000-01-15

申请号：KR1019980024691

申请日：1998-06-29

Applicant: 매그나칩 반도체 유한회사

Inventor： 배종홍

IPC: H03M1/16

CPC classification number: H03M1/462 ,  H03M2201/61

Abstract: PURPOSE: A device for converting an analog-digital and a converting method thereof are provided to reduce a converting time required for converting an analog signal to a digital signal to one cycle for converting efficiently in a short time. CONSTITUTION: A device for converting an analog-digital comprises: a storing instrument storing a digital standard signal; a digital-analog converting instrument(71) converting the digital standard signal to an analog signal for outputting an analog standard signal; and a comparing instrument comparing the analog standard signal inputted from the digital-analog converting instrument with an input analog signal inputted for converting for outputting the result of comparison.

Abstract translation: 目的：提供一种用于转换模拟数字及其转换方法的装置，以将将模拟信号转换为数字信号所需的转换时间减少到一个周期，以便在短时间内有效转换。 构成：用于转换模拟数字的装置包括：存储数字标准信号的存储装置; 将数字标准信号转换为模拟信号以输出模拟标准信号的数模转换仪器（71）; 以及将从数字 - 模拟转换装置输入的模拟标准信号与输入的模拟信号进行比较的比较装置，用于输出比较结果的转换。

公开(公告)号：KR101280876B1

公开(公告)日：2013-07-02

申请号：KR1020120008010

申请日：2012-01-26

Applicant: 주식회사 레이믹스

Inventor： 정성재 ,  이정은 ,  김진화 ,  이주호

IPC: H03M1/12 ,  H03M3/02

CPC classification number: H03M3/364 ,  H03M1/0607 ,  H03M1/12 ,  H03M1/50 ,  H03M3/458 ,  H03M2201/23 ,  H03M2201/61

Abstract: PURPOSE: A continuous time sigma-delta analog-to-digital (AD) converter is provided not to have an effect on the property of the loop filter even in case that the input terminal of sigma-delta AD converter and the common mode voltage of the amplifier of loop filter are different. CONSTITUTION: A loop filter (10) includes a first amplifier (11) amplifying a signal. A current control level shifter (40) controls a direct current, which is inputted to the positive input node voltage and negative input node voltage of the first amplifier, and shifts the positive input node voltage and negative input node voltage of the first amplifier. The current control level shifter shifts the positive input node voltage and negative input node voltage of the first amplifier, and fits the positive input node voltage and negative input node voltage of the first amplifier to the same value as the common mode voltage of the first amplifier. [Reference numerals] (10) Loop filter; (20) Quantization part; (30) Digital-analog conversion part; (40) Current control level shifter; (45) Current mirror

Abstract translation: 目的：提供连续时间Σ-Δ模数（AD）转换器，即使在Σ-ΔAD转换器的输入端和共模电压的情况下也不影响环路滤波器的性能 环路滤波器的放大器是不同的。 构成：环路滤波器（10）包括放大信号的第一放大器（11）。 电流控制电平移位器（40）控制输入到第一放大器的正输入节点电压和负输入节点电压的直流电，并移位第一放大器的正输入节点电压和负输入节点电压。 电流控制电平移位器移动第一放大器的正输入节点电压和负输入节点电压，并将第一放大器的正输入节点电压和负输入节点电压拟合到与第一放大器的共模电压相同的值 。 （附图标记）（10）环路滤波器; （20）量化部分; （30）数模转换部分; （40）电流控制电平转换器; （45）电流镜

公开(公告)号：KR1020130052916A

公开(公告)日：2013-05-23

申请号：KR1020110118255

申请日：2011-11-14

Applicant: 주식회사 실리콘웍스

Inventor： 김지훈 ,  손영준 ,  나준호 ,  배정열

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M2201/61 ,  H03M2201/62 ,  H03M2201/8152 ,  H03M2201/932

Abstract: PURPOSE: A digital analog converter which applies an electric charge subtraction method is provided to minimize errors of capacitors and relatively reduce a size of a decoder. CONSTITUTION: A control signal generating device(340) generates a switch control signal in response to digital data of N bits. A resistance string(310) comprises a first resistor array, a second resistor array, and a third resistor array which respectively divide multiple resistances which are connected between a reference voltage and a grounding voltage in series. A switch block(320) outputs a selection voltage by switching a part of voltage which is applied to any node of multiple serial resistances respectively included in the first resistor array, the second resistor array, and the third resistor array in response to the switch control signal. A conversion voltage generating block(330) generates a conversion voltage in response to a negative phase clock signal which is opposite to a positive phase clock signal.

Abstract translation: 目的：提供一种应用电荷减法的数字模拟转换器，以最小化电容器的误差并相对减小解码器的尺寸。 构成：响应于N位的数字数据，控制信号产生装置（340）产生开关控制信号。 电阻串（310）包括分别分别连接在参考电压和接地电压之间的多个电阻的第一电阻器阵列，第二电阻器阵列和第三电阻器阵列。 开关块（320）响应于开关控制切换施加到分别包括在第一电阻器阵列，第二电阻器阵列和第三电阻器阵列中的多个串联电阻的任何节点的电压的一部分来输出选择电压 信号。 转换电压产生块（330）响应于与正相位时钟信号相反的负相位时钟信号产生转换电压。

公开(公告)号：KR101160962B1

公开(公告)日：2012-06-29

申请号：KR1020110040171

申请日：2011-04-28

Applicant: 서강대학교산학협력단

Inventor： 이승훈 ,  구병우 ,  박혜림

IPC: H03M1/12

CPC classification number: H03M1/1245 ,  H03M1/0607 ,  H03M1/361 ,  H03M2201/2216 ,  H03M2201/61 ,  H03M2201/622 ,  H03M2201/643

Abstract: PURPOSE: An ADC(Analog To Digital Converter) for processing wideband variable input signals is provided to adopt all WUXGA(Wide Ultra Extended Graphics Array) resolutions from VGA(Video Graphics Array) by applying a second stage reference voltage selection method to a flash ADC. CONSTITUTION: A SHA(Sample-And-Hold Amplifier)(110) exactly samples values which are suitable for necessary specification by using GBC(Gate-Bootstrapping Circuit). A MDAC(Multiplying Digital-To-Analog Converter)(120) reduces the necessary number of unit capacitors by half since a merged-capacitor switching technique is applied. A FLASH1 ADC(Analog To Digital Converter)(130) and a FLASH2 ADC(140) apply an interpolation method. An on-chip reference current voltage generator(150) processes a broadband variable input signal through one external signal. A clock generator(160) generates non-overlapped two clocks from one reference clock, which is inputted from the outside, in a chip. A digital correction circuit(170) including the clock generator and a divider is integrated with an on-chip.

Abstract translation: 目的：提供用于处理宽带可变输入信号的ADC（模/数转换器），以通过将第二级参考电压选择方法应用于闪存ADC来采用VGA（视频图形阵列）中的所有WUXGA（Wide Ultra Extended Graphics Array） 。 构成：SHA（采样保持放大器）（110）通过使用GBC（栅极引导电路）精确地采样适合于必要规格的值。 使用合并电容切换技术，MDAC（乘法数模转换器）（120）将必需数量的单位电容器减少了一半。 FLASH1 ADC（模数转换器）（130）和FLASH2 ADC（140）应用插值方法。 片上参考电流电压发生器（150）通过一个外部信号处理宽带可变输入信号。 时钟发生器（160）从芯片中从外部输入的一个参考时钟产生非重叠的两个时钟。 包括时钟发生器和分频器的数字校正电路（170）与片上集成。