公开(公告)号：US08897051B2

公开(公告)日：2014-11-25

申请号：US14052864

申请日：2013-10-14

Applicant: J-Devices Corporation

Inventor： Satoru Itakura ,  Akio Katsumata ,  Akihiro Umeki ,  Yasushi Shiraishi ,  Junichiro Abe

IPC: G11C5/02 ,  G11C5/06 ,  G11C5/14 ,  G11C7/00 ,  G11C7/10 ,  G11C16/30 ,  G06F3/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L21/66 ,  G11C11/4096

CPC classification number: G11C16/30 ,  G06F3/00 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C7/10 ,  G11C7/1069 ,  G11C11/4096 ,  H01L22/10 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/19105

Abstract: A semiconductor storage device 100 includes a controller package 110 having a BGA terminal on a bottom surface thereof; and one or a plurality of memory packages 120 each including a plurality of semiconductor storage elements and mounted on the controller package. The controller package includes a bottom substrate having the BGA terminal on a bottom surface thereof; a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC. The controller provides an interface with an external system via the BGA terminal and controls a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements.

Abstract translation: 半导体存储装置100包括其底表面上具有BGA端子的控制器封装110; 每个包括多个半导体存储元件并安装在控制器封装上的一个或多个存储器封装120。 所述控制器封装包括在其底表面上具有所述BGA端子的底部基板; 电源IC，安装在底部基板上，用于供给多个电源; 以及控制器，其安装在所述底部基板上并且可由所述电源IC提供的所述多个电源操作。 控制器通过BGA端子提供与外部系统的接口，并控制来自半导体存储元件的读取操作和对半导体存储元件的写入操作。

公开(公告)号：US20140138852A1

公开(公告)日：2014-05-22

申请号：US14083834

申请日：2013-11-19

Applicant: J-DEVICES CORPORATION

Inventor： Toru SUDA

IPC: H01L23/31 ,  H01L25/00

CPC classification number: H01L23/3157 ,  H01L21/563 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/556 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/00 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06051 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/11462 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a rectangular lower semiconductor element; a plurality of external electrodes located in a pattern on the lower semiconductor element along sides thereof; a plurality of internal electrodes electrically connected to the plurality of external electrodes via a plurality of line patterns respectively and located on the lower semiconductor element in a pattern; dams provided in such a pattern that each of the dams encloses one or at least two external electrodes among the plurality of external electrodes; an upper semiconductor element mounted on the lower semiconductor element such that a plurality of terminals on the upper semiconductor element are electrically connected to the plurality of internal electrodes respectively; and a resin potted to flow to a space between the lower semiconductor element and the upper semiconductor element.

Abstract translation: 半导体器件包括矩形下半导体元件; 多个外部电极，沿其侧面位于下部半导体元件上的图案中; 多个内部电极经由多个线图案电连接到所述多个外部电极，并以图案位于所述下部半导体元件上; 堤坝以这样的图案提供，使得每个坝围绕多个外部电极中的一个或至少两个外部电极; 上半导体元件，其安装在所述下半导体元件上，使得所述上半导体元件上的多个端子分别电连接到所述多个内部电极; 以及被封装以流到下半导体元件和上半导体元件之间的空间的树脂。

公开(公告)号：US11189553B2

公开(公告)日：2021-11-30

申请号：US16661952

申请日：2019-10-23

Applicant: J-Devices Corporation

Inventor： Naoki Hayashi

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48

Abstract: Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via.

公开(公告)号：US20200066623A1

公开(公告)日：2020-02-27

申请号：US16661952

申请日：2019-10-23

Applicant: J-Devices Corporation

Inventor： Naoki HAYASHI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538

Abstract: Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via.

公开(公告)号：US10256196B2

公开(公告)日：2019-04-09

申请号：US15198785

申请日：2016-06-30

Applicant: J-DEVICES CORPORATION

Inventor： Kiminori Ishido ,  Michiaki Tamakawa ,  Toshihiro Iwasaki

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: A semiconductor device in which an insulating material layer contains no reinforced fibers such as a glass cloth or a nonwoven cloth and which enables miniaturization of metal thin-film wiring layers, a reduction in the diameter of metal vias, and a reduction in interlayer thickness. The semiconductor device includes an insulating material layer including one or more semiconductor elements sealed with an insulating material containing no reinforced fibers, a plurality of metal thin-film wiring layers, metal vias that electrically connect the metal thin-film wiring layers together and electrodes of the semiconductor elements and the metal thin-film wiring layers together, and a warpage adjustment layer arranged on one principal surface of the insulating material layer to offset warpage of the insulating material layer to reduce warpage of the semiconductor device.

公开(公告)号：US20180174975A1

公开(公告)日：2018-06-21

申请号：US15884979

申请日：2018-01-31

Applicant: J-Devices Corporation

Inventor： Toshiyuki INAOKA ,  Yuichiro YOSHIKAWA ,  Atsuhiro URATSUJI ,  Katsushi YOSHIMITSU

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L21/56

CPC classification number: H01L21/4871 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/15747

Abstract: An object of the present invention is to provide a semiconductor package with which it is possible to reduce a volume of an encapsulation resin and to easily embed a resin regardless of thicknesses of semiconductor chips and a small distance between adjacent semiconductor chips, as well as to provide a thin semiconductor package with which a final product includes no support flat plate. To realize this, a semiconductor package having a structure wherein semiconductor chips are accommodated in cavity parts of a support which is formed by copper plating and includes the cavity parts is provided.

公开(公告)号：US09922931B2

公开(公告)日：2018-03-20

申请号：US15419091

申请日：2017-01-30

Applicant: J-Devices Corporation

Inventor： Hiroaki Matsubara ,  Tomoshige Chikai ,  Naoki Hayashi ,  Toshihiro Iwasaki

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/538 ,  H01L21/768

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: An interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing the miniaturization of signal lines and increasing the film thickness. The interconnect structure includes a resin layer; and interconnects formed on the resin layer, wherein the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and the interconnects are formed of a plating film created on a resin layer front surface in the area, in which the interconnects are formed, and on inner wall surfaces of the plurality of grooves.

公开(公告)号：US09905536B2

公开(公告)日：2018-02-27

申请号：US14994963

申请日：2016-01-13

Applicant: J-DEVICES CORPORATION

Inventor： Makoto Moda

IPC: H01L25/065 ,  H01L23/36 ,  H01L23/498 ,  H01L29/06 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/36 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L29/0657 ,  H01L2224/05554 ,  H01L2224/26145 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/2939 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49173 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83365 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor device is provided including a package substrate, and a plurality of semiconductor chips stacked above the package substrate, at least one of the plurality of semiconductor chips including a step part in a periphery edge part of a rear surface.

公开(公告)号：US20170301599A1

公开(公告)日：2017-10-19

申请号：US15640071

申请日：2017-06-30

Applicant: J-DEVICES CORPORATION

Inventor： Takeshi MIYAKOSHI ,  Sumikazu HOSOYAMADA ,  Yoshikazu KUMAGAYA ,  Tomoshige CHIKAI ,  Shingo NAKAMURA ,  Hiroaki MATSUBARA ,  Shotaro SAKUMOTO

IPC: H01L23/31 ,  H01L23/467 ,  H01L23/473 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3135 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/467 ,  H01L23/473 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/17 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/16245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/73204 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the circuit board via a bump located between the power device and the circuit board; and a heat releasing member connected to the power device. The circuit board may be a multi-layer wiring board. The circuit board may include a capacitor element, a resistor element, an inductor element, a diode element and a switching element.

公开(公告)号：US09786611B2

公开(公告)日：2017-10-10

申请号：US15235439

申请日：2016-08-12

Applicant: J-DEVICES CORPORATION

Inventor： Kiyoaki Hashimoto ,  Yasuyuki Takehara

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/544 ,  H01L23/36 ,  H01L23/373 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0224 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/82

Abstract: A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of A, the stress relaxation layer has an elastic modulus of B, and the encapsulation material has an elastic modulus of C under a same temperature condition, the relationship of A>C>B or C>A>B is obtained.